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US 9,425,102 B2Granted
FinFETs with different fin heights
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTsung-Lin Lee, Chih Chieh Yeh, Chang-Yun Chang, Feng Yuan
Life of this patent
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Abstract
An integrated circuit structure includes a semiconductor substrate including a first portion in a first device region, and a second portion in a second device region. A first semiconductor fin is over the semiconductor substrate and has a first fin height. A second semiconductor fin is over the semiconductor substrate and has a second fin height. The first fin height is greater than the second fin height.
Claims20
A method comprising:
- forming a first shallow trench isolation (STI) region and a second STI region in a semiconductor substrate, the first STI region being in a first device region, and the second STI region being in a second device region;
- forming a first mask covering the second device region;
- recessing the first STI region to a first depth, a portion of the semiconductor substrate extending from the recessed first STI region forming a first semiconductor fin, the first depth being from a top surface of the first semiconductor fin to a top surface of the recessed first STI region;
- removing the first mask;
- forming a second mask covering the first device region;
- and
- recessing the second STI region to a second depth different from the first depth, a portion of the semiconductor substrate extending from the recessed second STI region forming a second semiconductor fin, the second depth being from a top surface of the second semiconductor fin to a top surface of the recessed second STI region, a portion of the semiconductor substrate being between the first semiconductor fin and the second semiconductor fin, top surfaces of the first semiconductor fin, the second semiconductor fin, and the portion of the semiconductor substrate being level with each other.
4 more elements
A method comprising:
- forming a first shallow trench isolation (STI) region and a second STI region in a semiconductor substrate, the first STI region being in a first device region, and the second STI region being in a second device region;
- doping the first STI region with a first impurity to a first impurity concentration;
- doping the second STI region with a second impurity to a second impurity concentration different from the first impurity concentration;
- and
- simultaneously recessing the first STI region and the second STI region, a portion of the semiconductor substrate extending from the recessed first STI region forming a first semiconductor fin, and a portion of the semiconductor substrate extending from the recessed second STI region forming a second semiconductor fin.
2 more elements
A method comprising:
- forming a first shallow trench isolation (STI) region and a second STI region in a semiconductor substrate, the first STI region being in a first device region, and the second STI region being in a second device region, a first portion of the semiconductor substrate extending from the first STI region forming a first semiconductor fin, and a second portion of the semiconductor substrate extending from the second STI region forming a second semiconductor fin, the first STI region having a first depth from a top surface of the first STI region to a bottom surface of the first STI region, the second STI region having a second depth from a top surface of the second STI region to a bottom surface of the second STI region, the second depth being different than the first depth, a portion of the semiconductor substrate being between the first semiconductor fin and the second semiconductor fin;
- forming a first gate dielectric and a second gate dielectric on top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, respectively;
- and
- forming a first gate electrode and a second gate electrode on the first gate dielectric and the second gate dielectric, respectively, the first semiconductor fin, the first gate dielectric, and the first gate electrode forming a first fin field-effect transistor (FinFET), and the second semiconductor fin, the second gate dielectric, and the second gate electrode forming a second FinFET.
1 more element
Dependencies are inferred from the claim text.