Epitaxial channel with a counter-halo implant to improve analog gain

A method, comprising:

• introducing dopant impurities of a first impurity type into first and second transistor regions of a substrate, wherein the first and second transistor regions comprise first and second channel regions and first and second source/drain regions, respectively;
• recessing the substrate over the first and second transistor regions;
• forming first and second layers of carbon-containing material over the first and second transistor regions;
• forming first and second layers of substrate material over the first and second layers of carbon-containing material;
• forming first and second gate dielectrics over the first and second layers of substrate material;
• forming first and second gate structures over the first and second gate dielectrics in the first and second channel regions, wherein the first gate structure is separated by a first horizontal space (s1) from a third gate structure, and wherein the second gate structure is separated by a second horizontal space (s2) from a fourth gate structure, and wherein s2 is greater than s1;
• performing a first implant at a first angle with a vertical line to introduce further dopant impurities of the first impurity type into the substrate at edges of the first and second channel regions;
• and
• performing a second implant at a second angle with the vertical line to introduce dopant impurities of a second impurity type, which is opposite the first impurity type, wherein the second angle is greater than a first threshold such that the second implant is blocked from reaching the first channel region by the third gate structure.

A method comprising:

• performing a well implant to introduce dopant impurities of a first impurity type into first and second transistor regions of a substrate;
• forming an epitaxial layer comprising carbon over the substrate;
• forming a plurality of first gate structures and a plurality of second gate structures over the epitaxial layer, respectively on the first and second transistor regions, wherein the plurality of first gate structures are separated by a first horizontal space (s1), wherein the plurality of second gate structures are separated by a second horizontal space (s2), which is greater than s1, and wherein the plurality of first and second gate structures share a common height (h);
• and
• performing a counter-halo implant to introduce dopant impurities of a second impurity type, opposite the first impurity type, into the second transistor region, wherein the counter-halo implant is performed at a first angle with respect to a vertical line in which the counter-halo implant is blocked from reaching the first transistor region by the plurality of first gate structures.