Distributed metal routing
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYou-Cheng Xiao, Yen-Huei Chen, Jung-Hsuan Chen, Shao-Yu Chou, Li-Chun Tien, Hung-Jen Liao
Life of this patent
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Abstract
A system and method for a distributed metal routing is disclosed. An embodiment comprises a metal_0 layer with a metal_1 layer overlying the metal_0 layer. The metal_1 layer comprises separate parallel lines, with lines having different signals being distributed across the metal_1 layer. Such a layout decreases the parasitic resistance within the metal_0 layer as it decreases the distance current travels. Additionally, the distributed layout in metal_1 allows connections to be made to a metal_2 layer without the need for a hammer head connection of vias.
Claims20
A method of making a semiconductor device, the method comprising:
- forming a first metal layer on and in contact with an active area of a substrate, the first metal layer comprising a first conductive region;
- forming a first contact plug and a second contact plug in contact with the first conductive region;
- and
- forming a second metal layer over the first contact plug and the second contact plug, the second metal layer comprising a first set of parallel lines coupled to a first source and a second set of parallel lines coupled to a second source, wherein the first set of parallel lines and the second set of parallel lines are interlaced with each other, and wherein a first one of the first set of parallel lines is coupled to the first contact plug and a second one of the first set of parallel lines is coupled to the second contact plug, wherein the first source is a varying signal source.
A method of making semiconductor device, the method comprising:
- forming a first conductive layer on a substrate, the first conductive layer comprising a first plurality of conductive lines and a second plurality of conductive lines, wherein the first plurality of conductive lines is parallel to and interleaved with the second plurality of conductive lines, at least some of the first plurality of conductive lines serving as gates for transistors formed in the substrate;
- and
- forming a second conductive layer over the first conductive layer and separated therefrom by a dielectric layer, the second conductive layer comprising a third plurality of conductive lines and a fourth plurality of conductive lines parallel to and interleaved with the third plurality of conductive lines, the third plurality of conductive lines and the fourth plurality of conductive lines being perpendicular to the first plurality of conductive lines and second plurality of conductive lines, wherein a first conductive line of the fourth plurality of conductive lines provides connection to signals to be distributed to multiple points on a second conductive line of the first plurality of conductive lines;
- and
- forming a plurality of interlayer interconnections, each of the plurality of interlayer interconnections extending through the dielectric layer from one of the first or second pluralities of conductive lines to one of the third or fourth plurality of conductive lines.
A method of making semiconductor device comprising:
- forming a plurality of devices in a substrate;
- forming a first conductive layer on a substrate, the first conductive layer comprising a first plurality of conductive lines and a second plurality of conductive lines, wherein the first plurality of conductive lines is parallel to and interleaved with the second plurality of conductive lines, at least some of the first plurality of conductive lines coupled to one or more of the plurality of devices;
- forming a second conductive layer over the first conductive layer and separated therefrom by a dielectric layer, the second conductive layer comprising a third plurality of conductive lines and a fourth plurality of conductive lines parallel to and interleaved with the third plurality of conductive lines, the third plurality of conductive lines and the fourth plurality of conductive lines being perpendicular to the first plurality of conductive lines and the second plurality of conductive lines, wherein the fourth plurality of conductive lines provides connection to signals to be distributed to multiple points on each the first plurality of conductive lines, the signals being non-power and non-ground signals;
- and
- forming a plurality of interlayer interconnections, each of the plurality of interlayer interconnections extending through the dielectric layer from one of the first or second pluralities of conductive lines to one of the third or fourth plurality of conductive lines.
Dependencies are inferred from the claim text.