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US 9,425,064 B2Granted
Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages
OwnerKarthik Thambidurai, Viren Khandekar +1inventors
InventorsKarthik Thambidurai, Viren Khandekar, Tiao Zhou
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Abstract
Techniques are described herein for a dip soldering process which provides a low-profile, low-cost solder bump formation process which may be implemented to promote package thickness scaling (e.g., reduce the overall package thickness). For example, the dip soldering process disclosed herein may enable ultra-thin wafer-level packages (WLP), ultra-thin wafer level quad-flat no-leads (WQFN) packages, or the like.
Claims15
A process comprising:
- positioning a plurality of semiconductor wafers over a receptacle, the plurality of semiconductor wafers disposed within a holder configured to hold the plurality of semiconductor wafers in a vertically oriented configuration, the receptacle containing liquid solder, wherein a flux is disposed over the receptacle, each semiconductor wafer of the plurality of semiconductor wafers further comprising silicon;
- prior to transitioning the plurality of semiconductor wafers through the flux and a solder bath, pre-heating respective semiconductor wafers of the plurality of semiconductor wafers to a temperature that is twenty to thirty degrees Celsius below a melting point of the liquid solder to minimize breakage of the respective semiconductor wafers of the plurality of semiconductor wafers;
- transitioning the plurality of semiconductor wafers through the flux to apply the flux to an underbump metallurgy of respective semiconductor wafers of the plurality of semiconductor wafers;
- transitioning the plurality of semiconductor wafers into the solder bath;
- placing the plurality of semiconductor wafers into the receptacle to coat the underbump metallurgy with the liquid solder;
- and
- removing the plurality of semiconductor wafers from the receptacle to allow the liquid solder coated on the underbump metallurgy to solidify and form a solder bump on the underbump metallurgy of the plurality of semiconductor wafers.
4 more elements
A process comprising:
- pre-heating a plurality of silicon wafers to a temperature of one hundred and fifty degrees Celsius prior to transitioning the plurality of silicon wafers through a flux to minimize breakage of the plurality of silicon wafers, the plurality of silicon wafers disposed within a holder configured to hold the plurality of silicon wafers in a vertically oriented configuration;
- positioning the plurality of silicon wafers over a receptacle, the receptacle containing liquid solder, wherein the flux is disposed over the receptacle;
- transitioning the plurality of silicon wafers through the flux to apply the flux to an underbump metallurgy of the plurality of silicon wafers, the plurality of silicon wafers transitioned through the flux at an angle of ninety degrees (90°) relative to a surface of the flux, the flux being one of:
- a liquid, a foam, or a paste;
- transitioning the plurality of silicon wafers through the flux into the receptacle to coat the underbump metallurgy with the liquid solder;
- removing the plurality of silicon wafers from the receptacle to allow the liquid solder coated on the underbump metallurgy to solidify and form a solder bump on the underbump metallurgy;
- and
- removing the flux from the plurality of silicon wafers.
5 more elements
Dependencies are inferred from the claim text.