Method and apparatus for manufacturing three-dimensional-structure memory device

A method for manufacturing a semiconductor device having a 3-dimensional structure, the method comprising:

• stacking a plurality of insulation layers and a plurality of sacrificial layers on a substrate alternately one another;
• forming a through hole passing through the insulation layers and the sacrificial layers;
• forming a pattern filling the through hole;
• forming an opening passing through the insulation layers and the sacrificial layers;
• and
• supplying an etchant through the opening to remove the sacrificial layers,
• wherein the stacking of the insulation layers is performed by supplying at least one first gas selected from the group comprising SiH4, Si2H6, Si3H8, and Si4H10 and at least one second gas selected from the group comprising an ethyl-based gas and methyl- based gas onto the substrate and by reacting the first gas and the second gas to deposit a silicon carbon oxide (SiCO),
• the stacking of the sacrificial layers is performed by supplying at least one third gas selected from the group comprising SiH4, Si2H6, Si3H8, and Si4H10, and dichlorosilane (SiCl2H2) and at least one fourth gas selected from the group comprising B2H6 and PH3 onto the substrate to deposit a silicon oxide in which boron or phosphorus is injected,
• the etchant comprises one of an HF solution and a buffered oxide etch (BOE) solution,
• the silicon carbon oxide (SiCO) of the insulation layers and the silicon oxide of the sacrificial layers have etch selectivity with respect to the etchant, and
• the silicon oxide of the sacrificial layers has an etch rate greater by about 5 times to about 300 times than that of the silicon carbon oxide (SiCO) of the insulation layers.