Block mask litho on high aspect ratio topography with minimal semiconductor material damage
AssigneeInternational Business Machines Corporation
InventorsMartin Glodde, Steven J. Holmes, Daiji Kawamura
Life of this patent
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Abstract
A trilayer stack that can be used as a block mask for forming patterning features in semiconductor structures with high aspect ratio topography is provided. The trilayer stack includes an organic planarization (OPL) layer, a titanium-containing antireflective coating (TiARC) layer on the OPL layer and a photoresist layer on the TiARC layer. Employing a combination of an OPL having a high etch rate and a TiARC layer that can be easily removed by a mild chemical etchant solution in the trilayer stack can significantly minimize substrate damage during lithographic patterning processes.
Claims19
A method of forming a semiconductor structure, comprising:
- forming a trilayer stack on an initial semiconductor structure formed on a substrate, the trilayer stack comprising an organic planarization layer (OPL), a titanium-containing antireflective coating (TiARC) layer on the OPL and a photoresist layer on the TiARC layer, wherein the TiARC layer comprises a Ti-containing organic inorganic hybrid polymer having a Ti-containing backbone with organic side chain functional groups;
- forming a pattern in the trilayer stack by etching through the trilayer stack to expose a portion of the initial semiconductor structure;
- and
- removing a remaining portion of the trilayer stack, wherein the removing the remaining portion of the trilayer stack causes no damage to a component of the semiconductor structure and the substrate, and wherein after the removing the remaining portion of the trilayer stack, substantially no residue from the trilayer stack remains in the semiconductor structure.
A method of forming a semiconductor structure, comprising:
- forming an initial semiconductor structure on a substrate, wherein the forming the initial semiconductor structure comprises:
- forming a plurality of sacrificial gate structures over a portion of each of semiconductor fins provided on the substrate, wherein the sacrificial gate structures are laterally bound by interlayer dielectric (ILD) layer portions,
- removing the sacrificial gate structures to provide gate cavities,
- forming a gate dielectric layer over surfaces of the gate cavities and top surfaces of the ILD layer portions, and
- forming a work function metal layer over the gate dielectric layer, wherein the work functional metal layer comprises TiN;
- forming a trilayer stack on the initial semiconductor structure, the trilayer stack comprising an organic planarization layer (OPL), a titanium-containing antireflective coating (TiARC) layer on the OPL and a photoresist layer on the TiARC layer;
- forming a pattern in the trilayer stack by etching through the trilayer stack to expose a portion of the initial semiconductor structure;
- and
- removing a remaining portion of the trilayer stack,
- wherein the removing the remaining portion of the trilayer stack causes no damage to a component of the semiconductor structure and the substrate, and wherein after the removing the remaining portion of the trilayer stack, substantially no residue from the trilayer stack remains in the semiconductor structure, and
- wherein the removing of the remaining TiARC layer removes a portion of the work function metal layer exposed by the patterned trilayer stack simultaneously.
Dependencies are inferred from the claim text.