US 9,425,048 B2 · Mechanisms for semiconductor device structure

Abstract

Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. Formation of voids, which tend to be formed in a rectangular hard mask structure, is prevented. In addition, formation of a self-aligned contact in the semiconductor device becomes easier, and risks of shortage between the contact and a metal gate structure in the semiconductor device decreased. In addition, a method for forming the semiconductor device structure is also provided. The method may include a gate last process.

Claims16

Dependent claims

A semiconductor device structure, comprising:

a substrate;
a metal gate structure formed over the substrate;
a spacer comprising an inner side and an outermost side, wherein the inner side is closer to the metal gate structure than the outermost side, wherein the inner side is formed on the metal gate structure;
and
a funnel shaped hard mask structure formed over and directly aligned with the metal gate structure, wherein a portion of a top surface of the funnel shaped hard mask structure extends horizontally past the outmost side of the spacer.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/073,408Filed 6 Nov 2013

Published

US 2015/0123175 A17 May 2015

Granted

23 Aug 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification15 codes

H10D 64/01326
Characterised by the conductor: aspects related to lithography, isolation or planarisation of the conductor
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 64/015
Manufacture or treatment: removing at least parts of gate spacers, e.g. disposable spacers
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…

Mechanisms for semiconductor device structure

Life of this patent

Mechanisms for semiconductor device structure

Life of this patent

Abstract

Claims16