Composite spacer for silicon nanocrystal memory storage

A memory device, comprising:

• a select gate disposed over a surface of a semiconductor substrate between a source region and a drain region that are laterally separated by a channel region arranged beneath the select gate;
• a control gate disposed along a lower portion of a sidewall surface of the select gate, and over the channel region between the select gate and the source;
• a charge-trapping layer disposed beneath the control gate and along the sidewall surface of the select gate, which separates the control gate from the select gate;
• a first nitride structure disposed over an upper surface of the control gate and laterally separated from the charge-trapping layer by a first vertically-oriented liner oxide layer disposed over the upper surface of the control gate;
• a second nitride structure disposed over the control gate and laterally separated from the first nitride structure;
• and
• a second vertically-oriented liner oxide layer laterally separated from the first vertically-oriented liner oxide layer by the first nitride structure and abutting a sidewall of the control gate.

A memory device, comprising:

• a semiconductor substrate comprising a source region and a drain region that are laterally separated by a channel region;
• a select gate disposed over the channel region;
• a control gate laterally offset from the select gate and vertically arranged over the channel region;
• a charge-trapping layer disposed beneath the control gate and between a first sidewall of the control gate and a first sidewall of the select gate;
• a first liner oxide layer that has an upper surface that is aligned with an upper surface of the select gate and that overlies an uppermost horizontal surface of the control gate;
• a first nitride structure disposed over the control gate and laterally separated from the select gate by the first liner oxide layer;
• a second nitride structure disposed over the control gate and laterally separated from the first nitride structure by a second liner oxide layer;
• and
• a first segment of tunnel oxide arranged along a second sidewall of the select gate opposite the first sidewall and having an upper surface aligned with an upper surface of the select gate.