Error correction code (ECC) selection using probability density functions of error correction capability in storage controllers with multiple error correction codes
AssigneeSeagate Technology LLC
InventorsYu Cai, Yunxiang Wu, Erich F. Haratsch
Life of this patent
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Abstract
An apparatus includes an error correction code circuit and an error correction code selection circuit. The error correction code circuit may be configured to encode and decode data using any of a plurality of error correction codes. The error correction code selection circuit may be configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode data responsive to one or more reliability statistics and predetermined data characterizing distribution properties of each of the plurality of error correction codes.
Claims20
An apparatus comprising:
- an error correction code circuit configured to encode and decode data using any of a plurality of error correction codes;
- and
- an error correction code selection circuit configured to control which of the plurality of error correction codes is used by the error correction code circuit to encode and decode the data in response to one or more reliability statistics and pre-characterized probability distributions of a number of errors that cause a first uncorrectable error correction code (UECC) failure for each of the plurality of error correction codes.
A method of selecting among a plurality of error correction codes of a storage controller comprising the steps of:
- determining a number of errors corrected during an error correction code decoding operation;
- and
- selecting one of the plurality of error correction codes based upon a result of comparing the number of errors corrected during the error correction code decoding operation and one or more parameters of pre-characterized probability distributions of a number of errors that cause a first uncorrectable error correction code (UECC) failure for each of the plurality of error correction codes.
An apparatus comprising:
- an interface configured to process a plurality of read/write operations to/from a memory;
- and
- a control circuit configured to control which of a plurality of error correction codes is used to encode and decode data in the memory in response to one or more reliability statistics and pre-characterized probability distributions of a number of errors that cause a first uncorrectable error correction code (UECC) failure for each of the plurality of error correction codes.
Dependencies are inferred from the claim text.