Back to results
US 9,419,031 B1Granted
Semiconductor and optoelectronic devices
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Deepak Sekar
Life of this patent
Estimating the term…
Abstract
An integrated device, including: a first mono-crystal layer including a plurality of image sensor pixels and alignment marks; an overlaying oxide on top of the first mono-crystal layer; and a second mono-crystal layer overlaying the oxide, where the second mono-crystal layer includes a plurality of single crystal transistors aligned to the alignment marks.
Claims20
An integrated device, comprising:
- an image sensor array and an image circuit array;
- wherein said image sensor array comprises a first mono-crystallized silicon layer, and said image circuit array comprises a second mono-crystallized silicon layer,
- wherein disposed between said first mono-crystallized silicon layer and said second mono-crystallized silicon layer is thin isolation layer, and
- wherein said first mono-crystallized silicon layer or said second mono-crystallized silicon layer thickness is less than 400 nm, and
- wherein said second mono-crystal layer comprises a plurality of single crystal transistors,
- wherein said image sensor array comprises a plurality of image sensor pixels,
- wherein said image sensor pixels and said single crystal transistors are aligned to each other.
4 more elements
An integrated device, comprising:
- an image sensor array and an image circuit array;
- wherein said image sensor array comprises a first mono-crystallized silicon layer, and said image circuit array comprises a second mono-crystallized silicon layer,
- wherein disposed between said first mono-crystallized silicon layer and said second mono-crystallized silicon layer is thin isolation layer, and
- wherein said first mono-crystallized silicon layer or said second mono-crystallized silicon layer thickness is less than 400 nm, and
- wherein said second mono-crystal layer comprises a plurality of single crystal transistors,
- wherein said second mono-crystal layer comprises two crystalline layers,
- wherein said two crystalline layers comprise a first transistors layer and a second transistors layer.
4 more elements
An integrated device, comprising:
- an image sensor array and an image circuit array;
- wherein said image sensor array comprises a first mono-crystallized silicon layer, and said image circuit array comprises a second mono-crystallized silicon layer,
- wherein disposed between said first mono-crystallized silicon layer and said second mono-crystallized silicon layer is a thin isolation layer,
- wherein said first mono-crystallized silicon layer or said second mono-crystallized silicon layer thickness is less than 400 nm, and
- wherein through said thin isolation layer are a multiplicity of conducting vias, and
- wherein said conducting vias have a diameter of less than 200 nm, and
- a third mono-crystallized silicon layer underlying said second mono-crystallized silicon layer,
- wherein said third mono-crystallized silicon layer comprises pixel electronics read-out and control circuits.
5 more elements
An integrated device, comprising:
- an image sensor array and an image circuit array;
- wherein said image sensor array comprises a first mono-crystallized silicon layer, and said image circuit array comprises a second mono-crystallized silicon layer,
- wherein disposed between said first mono-crystallized silicon layer and said second mono-crystallized silicon layer is thin isolation layer, and
- wherein said first mono-crystallized silicon layer or said second mono-crystallized silicon layer thickness is less than 400 nm, and
- a third mono-crystallized silicon layer underlying said first mono-crystallized silicon layer,
- wherein said third mono-crystallized silicon layer comprises pixel electronics read-out and control circuits.
3 more elements
Dependencies are inferred from the claim text.