Wrap around silicide for FinFETs
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
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Abstract
A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
Claims20
A method comprising:
- forming a gate stack on a middle portion of a semiconductor fin;
- forming a first gate spacer on a sidewall of the gate stack;
- after the first gate spacer is formed, forming a template dielectric region to cover the semiconductor fin;
- recessing the template dielectric region;
- after the recessing, forming a second gate spacer on the sidewall of the gate stack;
- etching an end portion of the semiconductor fin to form a recess in the template dielectric region;
- and
- epitaxially growing a source/drain region in the recess.
A method comprising:
- forming a gate stack on a middle portion of a semiconductor fin;
- forming a first gate spacer on a sidewall of the gate stack;
- after the first gate spacer is formed, forming a template dielectric region, with a top surface of the template dielectric region being substantially level with a top surface of the semiconductor fin;
- etching an end portion of the semiconductor fin to form a recess in the template dielectric region;
- epitaxially growing a source/drain region in the recess;
- removing at least a portion of the template dielectric region to expose sidewalls of the source/drain region;
- and
- siliciding the sidewalls of the source/drain region.
A method comprising:
- forming a gate stack on a middle portion of a semiconductor fin;
- forming a first gate spacer on a sidewall of the gate stack;
- depositing a template dielectric region, with both the semiconductor fin and the first gate spacer being embedded in the template dielectric region;
- etching back the template dielectric region to reveal the first gate spacer;
- performing an oxidation on the first gate spacer to oxidize a top portion of the first gate spacer;
- forming a second gate spacer on the sidewall of the gate stack;
- etching an end portion of the semiconductor fin to form a recess in the template dielectric region;
- and
- epitaxially growing a source/drain region in the recess.
Dependencies are inferred from the claim text.