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US 9,417,960 B2Granted
Preventing programming errors from occurring when programming flash memory cells
AssigneeSeagate Technology LLC
InventorsYu Cai, Yunxiang Wu, Zhengang Chen, Erich Haratsch
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Abstract
Mis-programming of MSB data in flash memory is prevented by using ECC decoding logic on the flash die that error corrects the LSB values prior to the LSB values being used in conjunction with the MSB values to determine the proper reference voltage ranges. Error correcting the LSB page data prior to using it in combination with the MSB page data to determine the reference voltage ranges ensures that the reference voltage ranges will be properly determined and programmed into the flash cells.
Claims21
A data storage system comprising:
- a host system;
- and
- a solid state drive (SSD) interfaced with the host system, the SSD including an SSD controller and at least one nonvolatile memory (NVM), the SSD controller including at least one SSD processor, a tier 1 error-correcting code (ECC) encoder/decoder, and a tier 2 ECC encoder/decoder, wherein the NVM includes at least a first flash memory having a plurality of flash memory cells, reference voltage range determination logic and tier 2 ECC decoding logic, the SSD controller receiving write data from the host system to be programmed into flash cells of the NVM, the write data comprising at least a first most significant bit (MSB) page of data and at least a first least significant bit (LSB) page of data, the tier 1 ECC encoder/decoder performing tier 1 ECC encoding of the first LSB page of data to produce a tier 1-encoded first LSB page of data, the tier 2 ECC encoder/decoder performing tier 2 ECC encoding of the tier 1-encoded first LSB page of data to produce a tier 1/tier 2-encoded first LSB page data, the SSD controller sending the tier 1/tier 2-encoded first LSB page of data to the first flash memory, the tier 1 ECC encoding/decoding logic performing tier 1 ECC encoding of the first MSB page of data to produce a tier 1-encoded first MSB page of data, the SSD controller sending the tier 1-encoded first MSB page of data to the first flash memory, the tier 1 ECC encoding and the tier 2 encoding being different types of encoding, the tier 2 decoding logic of the first flash memory being adapted to perform tier 2 decoding of LSB page data in the first flash memory.
A first flash memory integrated circuit (IC) die for use in a solid state drive (SSD) of a data storage system, the first flash memory IC die comprising:
- a plurality of flash memory cells for storing data;
- error-correcting code (ECC) decoding logic, the first flash memory IC die being configured to receive write data from an interface that interfaces an SSD controller of the SSD with the first flash memory IC die, the received write data comprising at least a first least significant bit (LSB) page of data and at least a first most significant bit (MSB) page of data, the first LSB page of data being encoded with a tier 1 ECC encoding and with a tier 2 ECC encoding, the first MSB page of data being encoded with the tier 1 encoding, the first flash memory IC die programming the first LSB page of data to a first LSB page of the flash memory cells, wherein prior to the first flash memory IC die programming the first MSB page of data to a first MSB page of the flash memory cells, the first flash memory IC die causes the encoded first LSB page of data to be read from the first LSB page of the flash memory cells and sent to the ECC decoding logic, and wherein the ECC decoding logic performs tier 2 ECC decoding of the encoded LSB page data to produce a tier 2-decoded first LSB page of data.
A method for programming data to flash memory of a data storage system, the method comprising:
- in a solid state drive (SSD) interfaced with a host system, receiving write data to be written to at least one nonvolatile memory (NVM), the write data comprising at least a first most significant bit (MSB) page of data and at least a first least significant bit (LSB) page of data, wherein the NVM includes at least a first flash memory having a plurality of flash memory cells, reference voltage range determination logic and tier 2 ECC decoding logic;
- in an SSD controller of the SSD, receiving the write data to be written to the NVM, the SSD controller including at least one SSD processor, tier 1 error-correcting code (ECC) encoder/decoder, and tier 2 ECC encoder/decoder;
- in the tier 1 ECC encoder/decoder, performing tier 1 ECC encoding of the first LSB page of data to produce a tier 1-encoded first LSB page of data;
- in the tier 2 ECC encoder/decoder, performing tier 2 ECC encoding of the tier 1-encoded first LSB page of data to produce a tier 1/tier 2-encoded first LSB page data;
- in the SSD controller, sending the tier 1/tier 2-encoded first LSB page of data to the first flash memory;
- in the tier 1 ECC encoder/decoder, performing tier 1 ECC encoding of the first MSB page of data to produce a tier 1-encoded first MSB page of data;
- and
- in the SSD controller, sending the tier 1-encoded first MSB page of data to the first flash memory, the tier 1 ECC encoding and the tier 2 encoding being different types of encoding.
5 more elements
Dependencies are inferred from the claim text.