Testing probe head for wafer level testing, and test probe card
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYung-Hsin Kuo, Wensen Hung, Po-Shi Yao
Life of this patent
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Abstract
A testing probe card for wafer level testing semiconductor IC packaged devices. The card includes a circuit board including testing circuitry and a testing probe head. The probe head includes a probe array having a plurality of metallic testing probes attached to a substrate including a plurality of conductive vias. In one embodiment, the probes have a relatively rigid construction and have one end that may be electrically coupled to the vias using a flip chip assembly solder reflow process. In one embodiment, the probes may be formed from a monolithic block of conductive material using reverse wire electric discharge machining.
Claims18
A testing probe head for wafer level testing comprising:
- a support substrate including a plurality of vias;
- and
- a probe array comprising a plurality of testing probes attached to and cantilevered from the support substrate, each of the plurality of testing probes electrically coupled to a respective via and arranged to engage a corresponding testing contact in a device under test,
- wherein the plurality of testing probes are configured to electrically contact the device under test for conducting wafer level testing;
- and
- at least one stopper, the stopper protruding laterally outwards from at least one of the plurality of testing probes, wherein one end of the at least one of the plurality of testing probes is configured to be inserted through an aperture in a guide plate spaced above the support substrate, and the stopper is engaged with the guide plate therein limiting an insertion depth of the at least one of the plurality of testing probes through the guide plate.
A testing probe head for wafer level testing comprising:
- a support substrate comprising silicon and including a plurality of through silicon vias (TSV);
- and
- a probe array comprising a plurality of rigid metallic testing probes attached to and cantilevered from the support substrate, each of the plurality of testing probes electrically coupled to a respective via and arranged to engage a corresponding testing contact in a device under test,
- wherein the plurality of testing probes are configured to electrically contact the device under test for conducting wafer level testing;
- and
- at least one stopper, the stopper protruding laterally outwards from at least one of the plurality of testing probes, wherein one end of the at least one of the plurality of testing probes is configured to be inserted through an aperture in a guide plate spaced above the support substrate, and the stopper is engaged with the guide plate therein limiting an insertion depth of the at least one of the plurality of testing probes through the guide plate.
A test probe card for wafer level testing comprising:
- a mounting assembly;
- a printed circuit board supported from the mounting assembly;
- and
- a testing probe head for wafer level testing comprising:
- a support substrate including a plurality of vias;
- and
- a probe array comprising a plurality of testing probes attached to and cantilevered from the support substrate, each of the plurality of testing probes electrically coupled to a respective via and arranged to engage a corresponding testing contact in a device under test,
- wherein the plurality of testing probes are configured to electrically contact the device under test for conducting wafer level testing;
- at least one stopper, the stopper protruding laterally outwards from at least one of the plurality of testing probes, wherein one end of the at least one of the plurality of testing probes is configured to be inserted through an aperture in a guide plate spaced above the support substrate, and the stopper is engaged with the guide plate therein limiting an insertion depth of the at least one of the plurality of testing probe through the guide plate.
Dependencies are inferred from the claim text.