Bit error pattern analyzer and method
AssigneeViavi Solutions Deutschland GmbH
InventorsReiner Schnizler, Paul Brooks
Life of this patent
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Abstract
The invention relates to a method and device for testing a data link. A single-lane or multi-lane bit error tester that transmits one or more PRBS signals through the data link is augmented with a raw bit error buffer for storing bit error information for each detected error event and an error pattern analyzer. Most frequently occurring intra-lane bit error patterns, inter-lane word error patterns, and bit slip patterns are identified and their characteristics are analyzed so as to provide information indicative of root causes of the detected bit errors and bit slips.
Claims19
A method of testing a data link having a multi-lane input port and a multi-lane output port, the method comprising:
- a) providing a first pseudo-random bit sequence (PRBS) and providing a second PRBS synchronously with the first PRBS to the multi-lane input port of the data link;
- b) using a first PRBS analyzer connected to the output port of the data link to detect bit error events in a first received bit sequence, wherein the first received bit sequence corresponds to the first PRBS transmitted over the data link, and using a second PRBS analyzer synchronized with the first PRBS analyzer to detect bit errors in a second bit sequence received at the multi-lane output port of the data link, wherein the second bit sequence corresponds to the second PRBS transmitted over the data link;
- c) for each bit error event detected by the first PRBS analyzer in at least a portion of the first received bit sequence and for each bit error event detected by the second PRBS analyzer in at least a portion of the second received bit sequence, writing bit error information into an error buffer, wherein the bit error information comprises PRBS analyzer state information corresponding to the detected bit error event, and generating, for each detected bit error event, a word error pattern identifier, said word error pattern identifier identifying an inter-lane word that is composed of bits from each of the first and second received bit sequences that are associated with the detected bit error event;
- d) using an error pattern analyzer to read the bit error information from the error buffer, to associate detected errors with specific bit patterns, and to generate therefrom error pattern analysis information that is indicative of a cause of the detected bit errors;
- and,
- e) providing the error pattern analysis information to a user.
A bit error pattern tester for testing digital signal transmission through a data link, comprising:
- a pseudo-random bit sequence (PRBS) generator for synchronously feeding PRBS signals into a multi-lane input port of the data link;
- PRBS analyzers for detecting bit errors in received bit sequences, wherein the received bit sequences correspond to the PRBS signals received from a multi-lane output port of the data link after transmission over the data link;
- an error data buffer;
- an error data generator operatively connected to the PRBS analyzers for receiving therefrom bit error information for each detected bit error event, and for writing the bit error information into the error buffer, and for generating, for each detected bit error event, a word error pattern identifier, said word error pattern identifier identifying an inter-lane word that is comprised of bits from the received bit sequences that are associated with the detected bit error event;
- an error pattern analyzer that is operatively connected to the error data buffer and is configured to associate detected errors with specific bit patterns based on the bit error information saved in the error data buffer, and to generate bit error pattern analysis information that is indicative of a cause of the detected bit errors;
- and,
- an output device for providing the bit error pattern analysis information to the user.
Dependencies are inferred from the claim text.