Chip or SoC including fusible logic array and functions to protect logic against reverse engineering

A security chip, comprising:

• an input configured to receive, from a verification module external to the security chip, a seed value, wherein the seed value corresponds to one of a predetermined value and a generated value;
• a fusible logic array configured to generate a logic result using the received seed value, wherein
• the fusible logic array includes a logic gate having structure corresponding to both i) a first type of logic gate configured to perform a first logic operation and ii) a second type of logic gate configured to perform a second logic operation different from the first logic operation,
• the logic gate includes a fusible link located within the logic gate, wherein the logic gate is configured to operate, based on a state of the fusible link, as both the first type of logic gate and the second type of logic gate, and wherein the fusible link is arranged to conceal which of the first type of logic gate and the second type of logic gate the logic gate is configured as, and
• the fusible logic array is configured to generate the logic result based on the state of the fusible link;
• and
• an output configured to provide a key value, representative of the logic result, to the verification module external to the security chip.