Aligned gate-all-around structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuo-Cheng Ching, Jean-Pierre Colinge, Zhiqiang Wu
Life of this patent
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Abstract
A semiconductor device includes a gate disposed over a substrate. The gate has a first gate portion of the gate including a gate dielectric and a gate electrode disposed above a first channel region and a second gate portion including a gate dielectric and a gate electrode disposed between the substrate and the first channel region and aligned with the first gate portion. A source and a drain region are disposed adjacent the gate. A dielectric layer is disposed on the substrate and has a first portion underlying at least some of the source, a second portion underlying at least some of the drain; and a third portion underlying at least some of the first channel, the first gate portion and the second gate portion.
Claims19
A semiconductor device, comprising:
- a gate disposed over a substrate, the gate having:
- a first gate portion of the gate including a gate dielectric and a gate electrode disposed above a first channel region;
- and
- a second gate portion including a gate dielectric and a gate electrode disposed between the substrate and the first channel region and aligned with the first gate portion;
- a source and a drain region adjacent the gate;
- and
- a dielectric layer on the substrate, wherein the dielectric layer has:
- a first portion underlying at least some of the source and laterally adjacent the gate dielectric of the second gate portion;
- a second portion underlying at least some of the drain and laterally adjacent the gate dielectric of the second gate portion;
- and
- a third portion underlying at least some of the first channel, the first gate portion and underlying and interfacing with the gate dielectric of the second gate portion.
A semiconductor device, comprising:
- a first gate portion of a gate structure disposed on a first channel region including a semiconductor material;
- a second gate portion of a gate structure disposed under the first channel region and aligned with the first portion, wherein the second gate portion includes a first gate dielectric layer and a first gate electrode layer disposed on a second channel region;
- a third gate portion of the gate structure disposed under the second channel and aligned with the second gate portion, wherein the third gate portion includes a second gate electrode layer disposed under the second channel region and a second gate dielectric layer disposed on a top surface, a bottom surface, and two opposing sidewalls of the second gate electrode layer;
- a first dielectric layer disposed adjacent each of two opposing sidewalls of the second portion of the gate structure having the first gate dielectric layer;
- and
- a second dielectric layer disposed vertically under the second channel region and horizontally adjacent each of the two opposing sidewalls of the third portion of the gate structure having the second gate dielectric layer.
A method for fabricating a semiconductor device, comprising:
- forming a semiconductor layer on a substrate upon which the semiconductor device is formed;
- forming a cavity within a semiconductor layer between a first channel region and the substrate, wherein the cavity is defined by a first lateral sidewall of the semiconductor layer and a second opposing lateral sidewall of the semiconductor layer, wherein the first and second lateral sidewalls are substantially perpendicular to a top surface of the substrate;
- oxidizing the first and second lateral sidewalls to form a first dielectric region and a second dielectric region the first dielectric region extending under at least some of a source region of the semiconductor device and the second dielectric region extending under at least some of a drain region of the semiconductor device;
- forming a first gate portion of a gate over the first channel region;
- and
- after the oxidizing, forming a second gate portion of the gate of the semiconductor device within at least some of the cavity, the second gate portion disposed between the substrate and the channel, the second gate portion aligned with a first gate portion of the gate above the channel, wherein forming the second gate portion after the oxidizing includes:
- forming an interfacial layer;
- depositing a high-k dielectric layer;
- and
- forming a metal gate stack.
Dependencies are inferred from the claim text.