Silicide regions in vertical gate all around (VGAA) devices and methods of forming same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKai-Chieh Yang, Wai-Yi Lien
Life of this patent
Estimating the term…
Abstract
An embodiment semiconductor device includes a nanowire extending upwards from a semiconductor substrate, a source/drain region in the nanowire, and a channel region in the nanowire over the source/drain region. The source/drain region further extends into the semiconductor substrate past edges of the nanowire. The semiconductor device further includes a gate structure encircling the channel region and a silicide in an upper portion of the source/drain region. A sidewall of the silicide is aligned with a sidewall of the gate structure.
Claims20
A method of forming a semiconductor device, the method comprising:
- forming a vertical gate all around (VGAA transistor), the VGAA transistor comprising:
- a first source/drain region, wherein the first source/drain region comprises:
- a first portion in a nanowire;
- and
- a second portion disposed at an upper surface of a semiconductor substrate;
- a channel region in the nanowire over the first portion of the first source/drain region;
- a second source/drain region in the nanowire over the channel region;
- and
- a gate structure encircling the channel region;
- after forming the gate structure, forming a silicide in the second portion of the first source/drain region;
- after forming the silicide, forming a first interlayer dielectric (ILD) over the silicide;
- and
- forming a source/drain contact extending through the first ILD and electrically connected to the silicide.
A method for forming a semiconductor device, the method comprising:
- forming a source/drain region, wherein the source/drain region comprises:
- a vertical portion in a nanowire;
- and
- a lateral portion extending laterally past the nanowire at an upper surface of a substrate;
- forming a channel region in the nanowire on the source/drain region;
- forming a gate structure around the channel region;
- partially exposing the lateral portion of the source/drain region, wherein partially exposing the lateral portion of the source/drain region comprises patterning the gate structure;
- forming a conductive film on the lateral portion of the source/drain region;
- performing an anneal on the conductive film to form a silicide in the source/drain region;
- after performing the anneal, forming an interlayer dielectric (ILD) over the silicide;
- and
- forming a source/drain contact extending through the ILD and electrically connected to the silicide.
A method comprising:
- patterning a multi-layered semiconductor substrate comprising a first semiconductor layer to define a nanowire, wherein after patterning, the first semiconductor layer comprises:
- a first portion in the nanowire;
- and
- a second portion extending laterally past the nanowire;
- forming a gate structure encircling the nanowire;
- exposing the second portion of the first semiconductor layer, wherein exposing the second portion of the first semiconductor layer comprises patterning the gate structure;
- depositing a conductive film on a top surface of the second portion of the first semiconductor layer;
- performing an anneal to form a silicide at the top surface of the second portion of the first semiconductor layer;
- and
- after forming the silicide, forming a first interlayer dielectric (ILD) over the silicide.
Dependencies are inferred from the claim text.