Reference line and bit line structure for 3D memory

A memory device, comprising:

• first and second stacks of conductive strips having sidewalls;
• a plurality of U-shaped films having outside surfaces contacting data storage structures on sidewalls of the first and second stacks;
• a plurality of first pads connected to ends of the U-shaped films in the plurality over the first stack and a plurality of second pads connected to the other ends of the U-shaped films in the plurality over the second stack;
• a first level of patterned conductors overlying the first and second stacks, the patterned conductors in the first level comprising a segment of a reference line and a plurality of inter-level connectors, the segment of the reference line connected to the first pads in the plurality, the inter-level connectors in the plurality connected to the second pads in the plurality;
• a second level of patterned conductors over the first level, the patterned conductors in the second level comprising a segment of a bit line, the segment of the bit line including a plurality of extensions contacting the inter-level connectors in the plurality;
• and
• a multilayered insulating structure over the first level, the multilayered insulating structure comprising a first insulating film, a second insulating film and a third insulating film, a respective one of the extensions in the plurality comprising a fin within the first and second insulating films.

A method of manufacturing a memory device, comprising:

• forming first and second stacks of conductive strips having sidewalls;
• forming data storage structures on the sidewalls of the first and second stacks;
• forming a plurality of U-shaped films on the data storage structures and between the stacks, a respective one of the U-shaped films in the plurality having a first pad over the first stack and a second pad over the second stack;
• depositing a first level of patterned conductors to provide a segment of a reference line connected to the first pad and an inter-level connector connected to the second pad;
• and
• depositing a second level of patterned conductors to provide a segment of a bit line, the segment of the bit line including an extension contacting the inter-level connector,
• wherein the extension comprises a fin having sides aligned with the segment of the bit line, and having other opposing sides aligned with a second insulating film.