Hybrid dielectric non-volatile memory with nano particles (Si/SiO2 core/shell) as charge trapping layer

Abstract

Si/SiO2 core/shell nanostructures with sizes below 30 nm as trapping points in UV curable hybrid organic-inorganic gate dielectrics are presented in order to investigate printable nano floating gate transistors. Not only does the novelty of this invention comes from fabricating high-quality hybrid organic/inorganic gate dielectric layer by Sol-Gel process at low temperature but also incorporating the monolayer of high-density of Si nanoparticles (NPs) without obvious interface defects and keeping the quality of dielectric layers. Fixed-charge trapping defects are successfully removed from hybrid dielectrics by UV curing together with low temperature thermal curing and mobile charges solely related to Si/SiO2 core/shell nanostructures on charge trapping layer clearly demonstrate memory effects on printable device. Thin/uniform SiO2 shell on each Si NP functions as tunneling layer of flash memory devices, significantly simplifying the fabrication of printable nano floating gate memory device.

Dependencies are inferred from the claim text.