Systems and methods for a signed magnitude adder in one's complement logic
AssigneeMarvell International Ltd.
InventorEngling Yeo
Life of this patent
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Abstract
Disclosed herein are systems and methods for a signed-magnitude adder based on one's complement logic, where the adder offers enhancements in both speed and chip area consumption. The one's complement based adder includes circuitry for converting operands from their signed-magnitude representations to their one's complement representations, circuitry for adding operands in their one's complement representations, and circuitry for converting the resulting sum into a signed-magnitude format.
Claims14
A method for adding a first operand in a first one's complement representation and a second operand in a second one's complement representation, the method comprising:
- converting the first and second operand from a first and second signed-magnitude representation to the first and second one's complement representation;
- generating a sum of the first one's complement representation and the second one's complement representation using a plurality of full adders followed by a half adder;
- determining whether the sum includes an overflow bit;
- removing the overflow bit from the sum in response to determining that the sum includes the overflow bit;
- adding the removed overflow bit to the sum at a least significant position of the sum using a plurality of half adders;
- and
- converting the sum to a signed-magnitude representation in response to determining that the sum is negative valued.
An adder for adding a first operand in a first one's complement representation and a second operand in a second one's complement representation, the adder comprising:
- first circuitry to convert the first and second operand from a first and second signed-magnitude representation to the first and second one's complement representation;
- second circuitry to generate a sum of the first one's complement representation and the second one's complement representation and to determine whether the sum includes an overflow bit, wherein the second circuitry comprises a plurality of full adders followed by a half adder;
- third circuitry to remove the overflow bit from the sum in response to determining that the sum includes the overflow bit;
- fourth circuitry to add the removed overflow bit to the sum at a least significant position of the sum, wherein the fourth circuitry comprises a plurality of half adders;
- and
- fifth circuitry to convert the sum to a signed-magnitude representation in response to determining that the sum is negative valued.
A device for adding a first operand in a first one's complement representation and a second operand in a second one's complement representation, the device comprising:
- means for converting the first and second operand from a first and second signed-magnitude representation to the first and second one's complement representation;
- means for generating a sum of the first one's complement representation and the second one's complement representation using a plurality of full adders followed by a half adder, and
- for determining whether the sum includes an overflow bit;
- means for removing the overflow bit from the sum in response to determining that the sum includes the overflow bit;
- means for adding the removed overflow bit to the sum at a least significant position of the sum using a plurality of half adders;
- and
- means for converting the sum to a signed-magnitude representation in response to determining that the sum is negative valued.
Dependencies are inferred from the claim text.