System and method for lifetime specific LDPC decoding

A nonvolatile memory controller for providing log likelihood ratios (LLRs) for low-density parity check (LDPC) decoding, the controller comprising:

• circuitry for storing a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of a nonvolatile memory storage module, each of the plurality of lifetime specific LLR look-up tables including LLRs representative of threshold voltage distributions of flash chips of the nonvolatile memory storage module at a point in the lifetime of the nonvolatile memory storage module;
• read circuitry for reading an LDPC encoded codeword stored in the nonvolatile memory storage module using a plurality of soft-decision reference voltages and for identifying a plurality of soft-decision bits representative of the codeword;
• circuitry for identifying a current point in the lifetime of the nonvolatile memory storage module based on the current bit error rate (BER) of one or more of the flash chips of the nonvolatile memory storage module;
• and
• circuitry for selecting a current lifetime specific LLR look-up table from the plurality of lifetime specific LLR look-up tables for the nonvolatile memory storage module based upon the identified current point in the lifetime of the nonvolatile memory storage module.

A nonvolatile memory controller for providing log likelihood ratios (LLRs) for low-density parity check (LDPC) decoding, the controller comprising:

• circuitry for storing a plurality of lifetime specific LLR look-up tables representative of the lifetime threshold voltage distribution of a nonvolatile memory storage module, each of the plurality of lifetime specific LLR look-up tables including LLRs representative of threshold voltage distributions of flash chips of the nonvolatile memory storage module at a point in the lifetime of the nonvolatile memory storage module, at least one of the plurality of lifetime specific LLR look-up tables representing each decade of bit error rate (BER) of the lifetime of the nonvolatile memory storage module;
• read circuitry for reading an LDPC encoded codeword stored in the nonvolatile memory storage module using a plurality of soft-decision reference voltages and for identifying a plurality of soft-decision bits representative of the codeword;
• circuitry for identifying a current point in the lifetime of the nonvolatile memory storage module based on the current bit error rate (BER) of one or more of the flash chips of the nonvolatile memory storage module;
• circuitry for selecting a current lifetime specific LLR look-up table from the plurality of lifetime specific LLR look-up tables for the nonvolatile memory storage module based upon the identified current point in the lifetime of the nonvolatile memory storage module;
• and
• circuitry to extract the LLRs from the current lifetime specific LLR look-up table for each of the soft-decision bits and to provide the extracted LLRs to an LDPC decoder for decoding of the codeword.

A nonvolatile memory system comprising:

• a nonvolatile memory storage module;
• read circuitry coupled to the nonvolatile memory storage module for reading a low-density parity check (LDPC) encoded codeword stored in the nonvolatile memory storage module using a plurality of soft-decision reference voltages and for identifying a plurality of soft-decision bits representative of the codeword;
• a plurality of lifetime specific log likelihood ratio (LLR) look-up tables representative of the lifetime threshold voltage distribution of the nonvolatile memory storage module, the plurality of lifetime specific LLR look-up tables stored in the nonvolatile memory system, each of the plurality of lifetime specific LLR look-up tables including a plurality of LLRs representative of a specific point in the lifetime of the nonvolatile memory storage module;
• circuitry coupled to the nonvolatile memory storage module for identifying a current point in the lifetime of the nonvolatile memory storage module based on the current BER of the nonvolatile memory storage module;
• circuitry for selecting a current lifetime specific LLR look-up table from the plurality of lifetime specific LLR look-up tables for the nonvolatile memory storage module based upon the identified current point in the lifetime of the nonvolatile memory storage module;
• and
• circuitry coupled to the nonvolatile memory storage module to extract the LLRs from the lifetime specific LLR look-up table for each of the soft-decision bits and to provide the extracted LLRs to an LDPC decoder for decoding of the codeword.