Dual path double zero continuous time linear equalizer

A method comprising:

• inputting a first signal at a transadmittance amplifier stage in a continuous time linear equalizer (CTLE), the transadmittance amplifier stage having first and second gain paths, wherein the second gain path comprises:
• a first capacitor disposed between an input of the first signal and a gate of a first transistor in the transadmittance amplifier stage;
• a second capacitor disposed between the input of the first signal and a gate of a second transistor in the transadmittance amplifier stage;
• and
• first and second resistors coupled between the gates of the first and second transistors, the first and second resistors further coupled to an output of an operational transconductance amplifier within the transadmittance amplifier stage;
• applying a DC gain recovery and a first high frequency gain to the first signal in the first gain path;
• applying a second high frequency gain to the first signal in the second gain path;
• generating, by the transadmittance amplifier stage, a second signal based on the DC gain recovery of the first signal and the first and second high frequency gains of the first signal, and outputting the second signal;
• and
• inputting, at a transimpedance amplifier stage, the second signal from the transadmittance amplifier stage, and converting the second signal to an output voltage signal.

A system comprising:

• a first line card and a second line card coupled to a backplane, wherein at least one of the first line card and the second line card comprises a continuous time linear equalizer (CTLE), the CTLE comprising:
• a transadmittance amplifier stage having first and second gain paths and configured to input a first signal and output a second signal, the first gain path configured to provide a DC gain recovery and a first high frequency gain to the first signal and the second gain path configured to provide a second high frequency gain to the first signal, the second signal generated by the transadmittance amplifier stage based on the DC gain recovery of the first signal and the first and second high frequency gains of the first signal, wherein the second gain path comprises:
• a first capacitor disposed between an input of the first signal and a gate of a first transistor in the transadmittance amplifier stage;
• a second capacitor disposed between the input of the first signal and a gate of a second transistor in the transadmittance amplifier stage;
• and
• first and second resistors coupled between the gates of the first and second transistors, the first and second resistors further coupled to an output of an operational transconductance amplifier within the transadmittance amplifier stage;
• and
• a transimpedance amplifier stage configured to input the second signal from the transadmittance amplifier stage and convert the second signal to an output voltage signal.