Semiconductor module
AssigneeNsk Ltd.
InventorsTakashi Sunaga, Noboru Kaneko, Osamu Miyoshi
Life of this patent
Estimating the term…
Abstract
A semiconductor module is provided for shortening a manufacturing tact time, reducing manufacturing costs and for ensuring reliability of a bonding portion. The semiconductor module includes a substrate formed of a metal, an insulating layer formed on the substrate, a plurality of wiring patterns formed on the insulating layer, a bare-chip transistor mounted on one wiring pattern via a solder, and copper connectors that connect electrodes formed on the bear-chip transistor and other wiring patterns via a solder. The copper connectors have a bridge shape, have a width-reduced portion formed in the vicinity of the bonding face to the electrodes, and have a stress-reducing portion formed on the bonding face bonded to the electrode.
Claims8
A semiconductor module comprising:
- a substrate formed of a metal;
- an insulating layer formed on the substrate;
- a plurality of wiring patterns formed on the insulating layer;
- a bare-chip transistor mounted on one of the plurality of wiring patterns via a solder;
- and
- a copper connector formed of a copper plate and connecting an electrode formed on a top surface of the bear-chip transistor and another one of the plurality of wiring patterns via a solder,
- wherein the copper connector includes a flat portion, a first leg portion folded downward extending from one end of the flat portion and bonded to the electrode, and a second leg portion folded downward extending from the other end of the flat portion and bonded to the another one of the plurality of wiring patterns to form a bridge shape,
- wherein a width-reduced portion having a width smaller than another part of the first leg portion is formed in the vicinity of the bonding face of the first leg portion bonded to the electrode, and a stress-reducing portion having a shape for reducing stress acting on the bonding face is formed on the bonding face of the first leg portion bonded to the electrode,
- wherein the bare-chip transistor is a bare-chip FET with a top surface on which a source electrode and a gate electrode are formed, the copper connector includes a source-electrode copper connector and a gate-electrode copper connector, top of the source electrode of the bare-chip FET and top of yet another one of the plural of wiring patterns are connected by the source-electrode copper connector via soldering, and a top of the gate electrode of the bare-chip FET and a top of further another one of the plural of wiring patterns are bonded by the gate-electrode copper connector via soldering, and
- wherein there is one type of the gate-electrode copper connector, and there are two types of the source-electrode copper connectors including a first source-electrode copper connector arranged 180° straightly with respect to the gate-electrode copper connector and a second source-electrode copper connector arranged 90° perpendicularly with respect to the gate-electrode copper connector, the one type of the gate-electrode copper connector and any one of the source-electrode copper connector of the two types of the first source-electrode copper connector or the second source-electrode copper connector are used in combination for the bare-chip FET.
Dependencies are inferred from the claim text.