Driver amplifier systems and methods of their operation

A radio frequency (RF) driver amplifier comprising:

• an input node coupled to an RF signal;
• an output node;
• a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the output node is coupled to the first source and the second drain, and wherein the input node is coupled to the second gate;
• a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the input node is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source;
• a fifth transistor comprising an n-type transistor having a fifth gate, fifth source and fifth drain;
• and
• a sixth transistor comprising an n-type transistor having a sixth gate, sixth source and sixth drain, and wherein:
• the input node is coupled to the second gate by coupling the sixth gate to the input node and coupling the sixth drain to the second gate;
• the input node is coupled to the third gate by coupling sixth drain to the fifth gate and coupling the fifth drain to the third gate;
• and
• the input node is coupled to the fourth gate by coupling sixth drain to the fourth gate.

A radio frequency (RF) driver amplifier comprising:

• an input node coupled to an RF signal;
• an output node;
• a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the output node is coupled to the first source and the second drain, and wherein the input node is coupled to the second gate;
• a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the input node is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source;
• a fifth transistor comprising an n-type transistor having a fifth gate, fifth source and fifth drain;
• a sixth transistor comprising an n-type transistor having a sixth gate, sixth source and sixth drain;
• a seventh transistor comprising an n-type transistor having a seventh gate, seventh source and seventh drain;
• and
• an eighth transistor comprising an n-type transistor having a eighth gate, eighth source and eighth drain, and wherein
• the input node is coupled to the second gate by coupling the sixth gate to the input node, coupling the sixth drain to the seventh gate, the seventh drain to the eighth gate, and the eighth drain to the second gate;
• the input node is coupled to the third gate by coupling sixth drain to the fifth gate and coupling the fifth drain to the third gate;
• and
• the input node is coupled to the fourth gate by coupling eighth drain to the fourth gate.

An amplifier comprising:

• a number, N, of switch-mode power amplifier (SMPA) branches, wherein N is greater than one, and wherein each SMPA branch includes:
• two drive signal inputs, so that the amplifier has a total of 2*N drive signal inputs,
• one SMPA branch output, so that the amplifier has a total of N SMPA branch outputs, and
• two driver amplifiers, each driver amplifier coupled to one of the two drive signal inputs, and wherein each of the two driver amplifiers includes:
• a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the corresponding SMPA branch output is coupled to the first source and the second drain, and wherein one of the corresponding drive signal inputs is coupled to the second gate;
• and
• a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the one of the corresponding drive signal inputs is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source, and wherein,
• in response to receiving a first combination of drive signals at the two drive signal inputs, each SMPA branch is configured to produce, at the SMPA branch output, an SMPA branch output signal at a first voltage level, and
• in response to receiving a different second combination of drive signals at the two drive signal inputs, each SMPA branch is configured to produce, at the SMPA branch output, the SMPA branch output signal at a different second voltage level.

A method, performed by an amplifier, for amplifying a time varying signal, the method comprising the steps of:

• receiving combinations of drive signals by a number, N, of switch-mode power amplifier (SMPA) branches of the amplifier, wherein N is greater than one, and wherein each SMPA branch includes two drive signal inputs, so that the amplifier has a total of 2*N drive signal inputs, and one SMPA branch output, so that the amplifier has a total of N SMPA branch outputs, and where each SMPA branch includes two driver amplifiers, each of the driver amplifiers including;
• a first transistor pair, the first transistor pair comprising a first transistor in series with a second transistor, the first transistor comprising an n-type transistor having a first gate, first source and first drain, the second transistor comprising an n-type transistor having a second gate, second source and second drain and wherein the corresponding SMPA branch output is coupled to the first source and the second drain, and wherein one of the corresponding drive signal inputs is coupled to the second gate;
• and
• a second transistor pair, the second transistor pair comprising a third transistor in series with a fourth transistor, the third transistor comprising an n-type transistor having a third gate, third source and third drain, the fourth transistor comprising an n-type transistor having a fourth gate, fourth source and fourth drain, and wherein the one of the corresponding drive signal inputs is coupled to the third gate and the fourth gate, and wherein the first gate is coupled to the third source, and wherein,
• in response to receiving a first combination of drive signals at the two drive signal inputs, producing, by each SMPA branch at the SMPA branch output, an SMPA branch output signal at a first voltage level;
• and
• in response to receiving a different second combination of drive signals at the two drive signal inputs, producing, by each SMPA branch at the SMPA branch output, the SMPA branch output signal at a different second voltage level.