US 9,391,070 B2Granted

Semiconductor device

AssigneeKabushiki Kaisha Toshiba

InventorsTomoko Matsudai, Tsuneo Ogura, Bungo Tanaka

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Abstract

A semiconductor device includes first electrode, first semiconductor layer of first conductivity type on the first electrode, second semiconductor layer of second conductivity type on the first semiconductor layer, third semiconductor layer of the first conductivity type on second semiconductor layer, fourth semiconductor layer of the second conductivity type selectively located on the third semiconductor layer, gate electrode through the third and fourth semiconductor layers and into the second semiconductor layer and insulated therefrom, second electrode on the fourth semiconductor layer, fifth semiconductor layer of the second conductivity type between the first electrode and the second semiconductor layer, sixth semiconductor layer of the first conductivity type on the second semiconductor layer contacting the second electrode, and seventh semiconductor layer of the first conductivity type in the second and sixth semiconductor layers, such that the bottom thereof is closer to the first electrode than the bottom of the gate insulating film.

Claims20

Dependent claims

A semiconductor device comprising:

a first electrode;
a first region including
a first semiconductor layer of a first conductivity type provided on the first electrode,
a second semiconductor layer of a second conductivity type provided over the first semiconductor layer,
a third semiconductor layer of the first conductivity type provided on the second semiconductor layer,
a fourth semiconductor layer of the second conductivity type selectively provided on the third semiconductor layer, and
a gate electrode extending through the third semiconductor layer and the fourth semiconductor layer and terminating inwardly of the second semiconductor layer, and separated from the second, third and fourth semiconductor layers by a gate insulating film;
a second electrode provided on the fourth semiconductor layer;
and
a second region adjacent to the first region, including
a fifth semiconductor layer of the second conductivity type provided between the first electrode and the second semiconductor layer and adjacent to the first semiconductor layer,
a sixth semiconductor layer of the first conductivity type provided on the second semiconductor layer in contact with the second electrode, and
a seventh semiconductor layer of the first conductivity type positioned in the second semiconductor layer and the sixth semiconductor layer such that the furthest extent thereof inwardly of the second semiconductor layer is closer to the first electrode than the bottom portion of the gate insulating film and the sixth semiconductor layer are.

10 more elements

A semiconductor RC-IGBT device formed on a substrate, comprising:

a first semiconductor layer of a first conductivity type having a first side and a second side;
a second semiconductor layer of a second conductivity type disposed on a first region of the first side of the first semiconductor layer;
a third semiconductor layer of a first conductivity type disposed on a second region of the first side of the first semiconductor layer which is physically different from the first region;
at least one gate trench extending inwardly of the second side of the first semiconductor layer;
a gate electrode disposed within the gate trench and spaced therefrom by a gate insulating layer, and the gate insulating layer spaced a first distance from the second side at the base of the trench;
a first anode layer of the second conductivity type, extending inwardly of the second surface of the first semiconductor layer by a second distance less than the first distance;
and
a second anode layer of the second conductivity type, extending inwardly of the second surface of the first semiconductor layer by a third distance greater than the first distance.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/633,051Filed 26 Feb 2015
Priority: JP 2014-18570611 Sep 2014
Published: US 2016/0079235 A117 Mar 2016
Granted: 12 Jul 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 8/00
Diodes
H10D 12/415
Insulated-gate bipolar transistors [IGBT]: having edge termination structures
H10D 12/416
Insulated-gate bipolar transistors [IGBT]: bidirectional devices, e.g. trench-gate IGBTs having additional gates at the anode side