Method to emulate message signaled interrupts with multiple interrupt vectors
AssigneeIntel Corporation
InventorYen Hsiang Chew
Life of this patent
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Abstract
Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device, and an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device.
Claims20
A processor, comprising:
- a memory decoder to monitor a predetermined memory location allocated to a device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device;
- and
- an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device.
A method, comprising:
- monitoring, by a memory decoder, a predetermined memory location allocated to a device;
- generating an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device;
- and
- issuing, by an interrupt controller in response to the emulated MSI signal generated by the memory decoder, an invocation for processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device.
The method of claimer 9, wherein the memory location is allocated from one of a cache memory associated with the execution unit and a system memory during initialization of the device.
The method of claimer 9, wherein the memory location is allocated from a processor cache associated with the execution unit, and wherein the interrupt data is stored in the memory location by the device via a direct cache access (DCA) transaction over a bus.
The method of claimer 9, wherein the interrupt data comprises data of a register, a first-in-first-out (FIFO), and/or a queue of the device representing a device control data, an address of a filled data buffer, an address of available device data for processing and/or an address of an available buffer to be filled.
A system, comprising:
- a bus;
- a device coupled to the bus;
- a memory decoder to monitor a predetermined memory location allocated to the device and to generate an emulated message signaled interrupt (MSI) signal in response to a posted write transaction to the predetermined memory location initiated from the device;
- and
- an interrupt controller, in response to the emulated MSI signal from the memory decoder, to invoke processing of a plurality of interrupts based on a plurality of interrupt vectors retrieved from the predetermined memory location, without receiving an actual MSI interrupt request from the device.
Dependencies are inferred from the claim text.