Circuits and methods of TAF-DPS vernier caliper for time-of-flight measurement

A system of measuring Time-of-Flight (TOF) between signal transitions of two electrical signals by using a plurality of clock generators, comprising:

• a first input for receiving an electrical signal Start;
• a second multi-bit input for receiving a plurality of q electrical signals Stop1, Stop2, . . . , Stopq where q is an integer of greater than zero;
• a third input for receiving a frequency control word Fslow;
• a fourth multi-bit input for receiving a plurality of q frequency control word Ffast_1, Ffast_2, . . . , Ffast_q;
• a fifth input for receiving an electrical signal of known frequency;
• a sixth input for receiving an enable signal;
• a multi-bit output for delivering TOF measurement result;
• a slow TAF-DPS clock generator for generating a slow clock signal, having a first input for receiving said Start signal, having a second input for receiving said frequency control word Fslow, having a first output for delivering said slow clock signal, having a second output for delivering an electrical signal for calibration;
• a plurality of q fast TAF-DPS clock generators for generating a plurality of q fast clock signals, each said fast TAF-DPS clock generator having a first input for receiving a Stop signal from said second multi-bit input, each said fast TAF-DPS clock generator having a second input for receiving a frequency control word Ffast from said fourth multi-bit input, each said fast TAF-DPS clock generator having a first output for delivering a fast clock signal, each said fast TAF-DPS clock generator having a second output for delivering an electrical signal for calibration;
• a plurality of q phase detectors for detecting a plurality of q point-of-coincidences, each said phase detector having a first input for receiving said slow clock signal, each said phase detector having a second input for receiving a said fast clock signal from one of said q fast TAF-DPS clock generators, each said phase detector having an output for delivering a reset signal;
• a plurality of q first digital counters, each said first digital counter having a clock input for receiving said slow clock signal, each said first digital counter having a reset input for receiving a said reset signal from one of said q phase detectors;
• each said first digital counter having an output for outputting its content;
• a plurality of q second digital counters, each said second digital counter having a clock input for receiving a said fast clock signal from one of said q fast TAF-DPS clock generators, each said second digital counter having a reset input for receiving a reset signal from one of said q phase detectors, each said second digital counter having an output for outputting its content;
• a calibration block, having an enable input for receiving a signal from said sixth input, having a calibration input for receiving a signal from said fifth input, having a first oscillation input for receiving signal from said second output of said slow TAF-DPS clock generator, having a multi-bit second oscillation input for receiving signals from said second outputs of said plurality of q fast TAF-DPS clock generators, having an output for delivering calibration result;
• a calculation block, having a plurality of q first inputs for receiving a plurality of q first digital values, having a plurality of q second inputs for receiving a plurality of q second digital values, having a third input for receiving a third digital value, having a multi-bit output for delivering calculation result;
• wherein said multi-bit output of calculation block is connected to said multi-bit output;
• wherein said output of each said first digital counter is connected to each said first input of calculation block;
• wherein said output of each said second digital counter is connected to each said second input of calculation block;
• wherein said output of calibration block is connected to said third input of calculation block.

A method of measuring TOF between signal transitions of a first and a second electrical signals, comprising the steps of:

• receiving a first electrical signal;
• receiving a plurality of q second electrical signals where q is an integer of greater than zero;
• creating a slow clock signal generator and a plurality of q fast clock signal generators by using gated ring oscillators and TAF-DPS frequency synthesizers and 1×PLLs;
• configuring said slow clock signal generator by using a frequency control word Fslow so that its output frequency (period) is set to be 1/f1=T1=Fslow·Δ=I·Δ where Δ is a base time unit and I is an integer of greater than one, configuring said fast clock signal generators by using a plurality of frequency control word Ffast_i so that their output frequencies (periods) are set to be 1/f2_i=T2_i=Ffast_i·Δ=[(I−1)+ri]·Δ, and ri is a fraction in range of [0,1), i=1, 2, . . . , q;
• starting the slow clock generator from rising (or falling) edge of said first electrical signal and generating a slow clock signal, starting each fast clock generator of said plurality of q fast clock generators from rising (or falling) edge of a second electrical signal from said plurality of q second electrical signals, generating a plurality of q fast clock signals from said q fast clock generators;
• feeding said slow clock signal and said plurality of q fast clock signals to a plurality of q phase detectors, driving a plurality of q first digital counters by said slow clock signal, driving each one of a plurality of q second digital counters by a said fast clock signal from said plurality of q fast clock signals;
• generating a plurality of q reset signals from said phase detectors by detecting a plurality of q point-of-coincidences, reading out contents of said plurality of q first and second digital counters after said plurality of q reset signals are received by said plurality of q first and second digital counters and then resetting said digital counters;
• calibrating the frequency of said gated ring oscillators;
• calculating TOFs between said first and a plurality of q second electrical signals.