System, apparatus, and method for sense amplifiers
AssigneeQUALCOMM Incorporated
InventorsSeong-Ook Jung, Taehui Na, Jisu Kim, Jung Pill Kim, Seung Hyuk Kang
Life of this patent
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Abstract
An offset cancelling sense amplifier according to some examples of the disclosure may use a double sensing margin structure and positive feedback to achieve better performance characteristics and read stability without a multistage operation. For example, a sense amplifier may include a second pair of sensing switches cross coupled in parallel with a first pair of sensing switches and a pair of degeneration transistors coupled in line before a pair of load transistors.
Claims26
A sense amplifier circuit for improving sensing margin and speed, comprising:
- a pair of degeneration transistors, a gate of each of the pair of degeneration transistors being selectively coupled to a ground and a supply voltage;
- a pair of load transistors coupled to the pair of degeneration transistors;
- a pair of capacitors, each of the pair of capacitors being coupled to a drain of one of the pair of load transistors and a gate of the other of the pair of load transistors;
- a first pair of sensing switches, each of the first pair of sensing switches being coupled to the gate of one of the pair of load transistors and the drain of a same one of the pair of load transistors;
- a second pair of sensing switches, each of the second pair of sensing switches being coupled to the drain of one of the pair of load transistors;
- and
- a third pair of sensing switches configured in parallel with the second pair of sensing switches, each of the third pair of sensing switches being coupled to the drain of one of the pair of load transistors and cross coupled below an opposite one of the second pair of sensing switches.
A current sensing circuit for a memory cell, comprising:
- a first degeneration transistor coupled to a bit line of a memory cell, the first degeneration transistor having a gate selectively coupled to a ground and a supply voltage;
- a second degeneration transistor coupled to a dummy bit line of the memory cell, the second degeneration transistor having a gate selectively coupled to a ground and the supply voltage;
- a first switch coupled to the bit line between the first degeneration transistor and the memory cell, the first switch configured to turn on the bit line;
- a second switch coupled to the dummy bit line between the second degeneration transistor and the memory cell, the second switch configured to turn on the dummy bit line;
- a third switch coupled to the bit line between the first degeneration transistor and the first switch and coupled to the dummy bit line between the second switch and the memory cell;
- and
- a fourth switch coupled to the dummy bit line between the second degeneration transistor and the second switch and coupled to the bit line between the first switch and the memory cell.
A method for sampling and amplifying a current in a read circuit of a memory cell, the method comprising:
- closing a first switch in a bit line, a second switch in a dummy bit line, a third switch between the bit line and a gate of a first load transistor, and a fourth switch between the dummy bit line and a gate of a second load transistor;
- opening a fifth switch coupled to the bit line between the first switch and a drain of the first load transistor and coupled to the dummy bit line between the second switch and a memory cell;
- and
- opening a sixth switch coupled to the dummy bit line between the second switch and a drain of the second load transistor and coupled to the bit line between the first switch and the memory cell.
Dependencies are inferred from the claim text.