Wireline receiver circuitry having collaborative timing recovery

An apparatus comprising:

• receiver lanes, each of the receiver lanes including a decision feedback equalizer to sample an input signal to provide data information and phase error information associated with clock signals used to sample the input signal;
• a combiner to combine the phase error information from each of the receiver lanes to provide bundled phase error information;
• and
• a controller to provide control information, generated based on the bundled phase error information, to each of the receiver lanes to control timing of the clock signals, wherein each of the receiver lanes includes:
• a lane proportional controller to provide an additional control information based on the phase error information;
• and
• a selector to select one of the control information generated based on the bundled phase error information and the additional control information to generate a selected control information in order to control timing of the clock signals based on the selected control information.

A method comprising:

• receiving an input signal at a decision feedback equalizer;
• sampling the input signal based on timing of clock signals to provide data information;
• conditionally obtaining phase error information based on values of three consecutive bits of the data information;
• and
• controlling timing of the clock signals based on the phase error information, wherein the decision feedback equalizer is included in a receiver lane among receiver lanes of a receiver, the receiver lane including a lane proportional controller and a selector, the lane proportional controller providing first control information based on the phase error information, the selector selecting one of the first control information and a second control information generated based on bundled phase error information to generate a selected control information in order to control timing of the clock signals based on the selected control information, wherein the bundled phase error information is provided by a combiner based on a combination of phase error information from each of the receiver lanes.

An electronic system comprising:

• conductive lines on a circuit board;
• a first device coupled to the conductive lines;
• and
• a second device coupled to the conductive lines, the second device including a receiver to receive signals transmitted on the conductive lines by the first device, the receiver including a decision feedback equalizer (DFE) having DFE slices, the DFE slices including a number of data comparators to provide data information based on sampling of one of the signals, and a number of phase error comparators to provide phase error information associated with clock signals used in the sampling, wherein the number of phase error comparators in the DFE slices is less than the number of data comparators of the DFE slices, wherein the DFE slices include a first DFE slice and a second DFE slice, and wherein:
• the first DFE slice includes two data comparators among the number of data comparators and one phase error comparator among the number of phase error comparators, each of the two data comparators of the first DFE slice including an input coupled to an input of the phase error comparator of the first DFE slice to receive a same signal as the phase error comparator of first DFE slice;
• and
• the second DFE slice includes two data comparators among the number of data comparators and one phase error comparator among the number of phase error comparators, each of the two data comparators of the second DFE slice including an input coupled to an input of the phase error comparator of the second DFE slice to receive a same signal as the phase error comparator of second DFE slice.