# US 9,362,974 B2 · Methods and systems for high bandwidth chip-to-chip communications interface

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- Number: US 9,362,974 B2
- Document ID: US9362974B2
- Status: Granted
- Kind: B2
- Application number: 14/823,870
- Filed: 2015-08-11
- Published: 2015-12-03
- Granted: 2016-06-07
- Earliest claimed: 2013-02-11
- Assignees: Kandou Labs, S.A.
- Applicants: Kandou Labs S.A.
- Inventors: John Fox; Brian Holden; Peter Hunt; John D. Keay; Amin Shokrollahi; Andrew Kevin John Stewart; Giuseppe Surace; Roger Ulrich; Richard Simpson
- Web page: https://patentgrep.com/patent/US9362974B2

## CPC

- H03K 19/018521: {of complementary type, e.g. CMOS}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- H03K 3/037: Bistable circuits
- H03K 19/017509: {Interface arrangements}
- H04B 1/40: Circuits
- H04L 67/12: specially adapted for proprietary or special-purpose networking environments, e.g. medical networks, sensor networks, networks in vehicles or remote metering networks
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/655: Fan-out layouts
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04B: TRANSMISSION
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Systems and methods are described for transmitting data over physical channels to provide a high bandwidth, low latency interface between integrated circuit chips with low power utilization. Communication is performed using group signaling over multiple wires using a vector signaling code, where each wire carries a low-swing signal that may take on more than two signal values.

## Claims

### Claim 1

An apparatus comprising:
a multi-wire bus configured to receive a set of N signals corresponding to N elements of a code word, wherein the elements of the code word comprise a set of at least three values, wherein the code word represents a set of n input bits, wherein n is an integer greater than 1 and N<2n;
a reference-less line receiver comprising a set of n+1 comparators, the set of n+1 comparators configured to operate on the received set of signals and responsively form a set of n+1 comparator outputs based on the received signals, wherein at least two comparators receive a common signal of the received set of N signals; and,
a decoder configured to receive the set of n+1 comparator outputs and responsively generate a set of n output bits representing the set of n input bits.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein 5 comparator outputs are decoded to generate 5 output bits.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the code word is balanced.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the set of at least three values comprises the set of values consisting of {−1, 0, +1}.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein each value of each element of the code word corresponds to a voltage that is less than a voltage Vdd supplied by a power source.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein at least one element corresponds to a voltage of ½*Vdd.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein at least one element corresponds to a voltage of ¼*Vdd.

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein 4 comparator outputs are decoded to generate 3 output bits.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein each received signal is terminated to a termination voltage Vt using a termination resistor.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein Vt corresponds to system ground.

### Claim 11 (depends on 1)

The apparatus of claim 1, wherein each received signal is terminated to a common node using a termination resistor.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the decoder comprises combinatorial logic to decode the set of n comparator outputs.

### Claim 13 (depends on 1)

The apparatus of claim 1, further comprising:
a plurality of wires configured to receive the set of n input bits representing the set of n output bits;
an encoder configured to generate the elements of the code word; and,
a transmit driver configured to transmit each respective element of the code word on a respective output wire of a set of output wires.

### Claim 14 (depends on 13)

The apparatus of claim 13, wherein for each respective element of the code word to be transmitted, the transmit driver comprises:
a voltage source configured to provide a signal level corresponding to a middle signal level on the respective output wire of the set of output wires;
a first transistor configured to receive a first input signal of a respective pair of input signals, the respective pair of input signals corresponding to a value of the respective element of the code word, wherein the first transistor is configured to provide a positive signal level to the output wire if the first input signal is high and provides no contribution otherwise; and,
a second transistor configured to receive a second input signal of the respective pair of input signals and provide a negative signal level to the output wire if the second input signal is high and no contribution if otherwise, wherein only one input signal of the respective pair of input signals can be high at one time.

### Claim 15 (depends on 14)

The method of claim 14, wherein the middle signal level corresponds to a quiescent signal level.

### Claim 16

A method comprising:
receiving a set of N signals corresponding to N elements of a code word, the elements of the code word comprising a set of at least three values, the code word representing a set of n input bits, wherein n is an integer greater than 1 and N<2n;
operating on the N received signals using a set of n+1 comparators and responsively forming a set of n+1 comparator outputs based on the received signals, wherein at least two comparators receive a common signal of the received set of N signals; and,
decoding the set of n+1 comparator outputs into a set of n output bits representing the n input bits.

### Claim 17 (depends on 16)

The method of claim 16, wherein decoding the set of n+1 comparator outputs comprises using a combinatorial logic decoder.

### Claim 18

A method comprising:
receiving a set of n input bits representing information, wherein n is an integer greater than 1;
generating elements of a code word based on the received set of n input bits; and, for each element of the code word:
forming a respective pair of driver signals corresponding to a value of a respective element of the code word, wherein at most one driver signal of the respective pair can be high at any time; and,
generating a signal level on a respective output wire of a set of output wires based on the respective pair of driver signals.

### Claim 19 (depends on 18)

The method of claim 18, wherein each driver signal of each respective pair of driver signals controls a respective transistor of a pair of transistors to provide a positive or negative signal level to the respective output wire.

### Claim 20 (depends on 19)

The method of claim 19, wherein the positive or negative signal level is contributed by sourcing or sinking current, respectively.