US 9,362,180 B2Granted

Integrated circuit having multiple threshold voltages

AssigneeGlobalfoundries Inc.

InventorsBongki Lee, Jin Ping Liu, Manoj Joshi, Manfred Eller, Rohit Pal, Richard J. Carter, Srikanth Balaji Samavedam

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Abstract

In one aspect there is set forth herein an integrated circuit having a first plurality of field effect transistors and a second plurality of field effect transistor, wherein field effect transistors of the first plurality of field effect transistors each have a first gate stack and wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack, the second gate stack being different from the first gate stack by having a metal layer common to the first gate stack and the second gate stack that includes a first thickness at the first gate stack and a second thickness at the second gate stack.

Claims20

Dependent claims

An integrated circuit comprising:

a substrate structure;
a first plurality of field effect transistors formed in the substrate structure, a second plurality of field effect transistors formed in the substrate structure, a third plurality of field effect transistors formed in the substrate structure, and a fourth plurality of field effect transistors formed in the substrate structure;
wherein field effect transistors of the first plurality of field effect transistors each have a first channel polarity and a first gate stack comprising a dielectric layer, a first conductive cap layer overlying the dielectric layer, a second conductive cap layer overlying the first cap layer, a first work function layer overlying the second conductive cap layer, and a metal layer overlying the first work function layer;
wherein field effect transistors of the second plurality of field effect transistors each have a second gate stack that comprises the layers of the first gate stack and the first channel polarity, the first conductive cap layer including a first thickness at the first gate stack and a second thickness at the second gate stack, wherein the second thickness is different from the first thickness;
wherein field effect transistors of the third plurality of field effect transistors each have a third gate stack and a channel polarity opposite the first channel polarity, the third gate stack comprising the layers of the first and second gate stacks and a second work function layer positioned between the second conductive cap layer and the first work function layer;
wherein field effect transistors of the fourth plurality of field effect transistors each have a fourth gate stack that comprises the layers of the third gate stack and a channel polarity opposite the first channel polarity, the first conductive cap layer including the first thickness at the fourth gate stack and the second thickness at the third gate stack;
wherein the second gate stack has a gate material sequence in common with the first gate stack, wherein the fourth gate stack has a gate material sequence in common with the third gate stack, and wherein the third gate stack has a gate material sequence that is different from a gate material sequence of the first gate stack;
wherein field effect transistors of the first plurality of field effect transistors each have a first Vt, and wherein field effect transistors of the second plurality of field effect transistors each have a second Vt, the second Vt being different from the first Vt.

5 more elements

A method for fabricating an integrated circuit, the method comprising:

depositing a plurality of gate stack layers, wherein the depositing includes varying a depositing of gate stack layers between first, second, third and fourth regions of a substrate structure so that there is defined at the first region of the substrate structure a first gate stack of a first field effect transistor having a first channel polarity and further so that there is defined at the second region of the substrate structure a second gate stack of a second field effect transistor having the first channel polarity and further so that there is defined at the third region of the substrate structure a third gate stack of a third field effect transistor having a second channel polarity opposite the first channel polarity and further so that there is defined at the fourth region of the substrate structure a fourth gate stack of a fourth field effect transistor having the second channel polarity,
wherein the first gate stack and the second gate stake comprise a dielectric layer, a first conductive cap layer overlying the dielectric layer, a second conductive cap layer overlying the first conductive cap layer, a first work function layer overlying the second conductive cap layer, and a metal layer overlying the first work function layer, and wherein the third gate stack and the fourth gate stake comprise the dielectric layer, the first conductive cap layer overlying the dielectric layer, the second conductive cap layer overlying the first conductive cap layer, the first work function layer overlying the second conductive cap layer, a second work function layer underlying the first work function layer and the metal layer overlying the second work function layer;
wherein the depositing is performed so that the first conductive cap layer includes a first thickness at the first gate stack and the third gate stack and a second thickness at the second gate stack and the fourth gate stack, wherein the second thickness is different from the first thickness;
wherein the depositing is performed so that the second gate stack has a gate material sequence in common with the first gate stack, wherein the fourth gate stack has a gate material sequence in common with the third gate stack, and wherein the third gate stack has a gate material sequence that is different from a gate material sequence of the first gate stack;
wherein the fabricating is performed so that the first field effect transistor includes a first threshold voltage and further so that the second field effect transistor includes a second threshold voltage, the second threshold voltage being different from the first threshold voltage.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/189,085Filed 25 Feb 2014
Published: US 2015/0243563 A127 Aug 2015
Granted: 7 Jun 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 64/667
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor comprising a layer of…
H10D 84/014
Manufacturing their gate conductors: the gate conductors having different materials or different implants
H10D 84/0158
The components including insulated gates, e.g. IGFETs: the components including FinFETs