Nanowire or 2D material strips interconnects in an integrated circuit cell
AssigneeSynopsys, Inc.
InventorsVictor Moroz, Jamil Kawa
Life of this patent
Estimating the term…
Abstract
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described.
Claims26
A computer system adapted to process a computer implemented representation of a circuit design, comprising:
- a processor and a memory coupled to the processor, the memory storing instructions that, when executed by the processor, cause the processor to select cells from a cell library;
- the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language;
- and
- at least one entry in the cell library comprising a specification of physical structures and timing parameters of a circuit including:
- a first transistor,
- a second transistor, and
- an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel,
- wherein said one or more nanowires or 2D material strips of the interconnect includes/include a set of nanowires or 2D material strips disposed in a plurality of stacks.
A computer program product, comprising:
- a memory device having stored thereon a machine readable specification of a cell, the specification of the cell including computer readable parameters specifying structural features of a physical implementation of a circuit, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components, the circuit comprising:
- a first transistor,
- a second transistor, and
- an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel,
- wherein said one or more nanowires or 2D material strips of the interconnect includes/include a set of nanowires or 2D material strips disposed in a plurality of stacks.
A method for designing a circuit, comprising:
- specifying a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel, to form a machine readable specification of circuit structures;
- executing a process utilizing the machine readable specification of circuit structures to determine parameters used to simulate timing characteristics of a physical implementation of the circuit when placed with other circuits or components;
- creating a machine readable specification of a cell including said parameters, the specification being executable by a computer running a placement process to control physical placement of the circuit with other circuits or components;
- and
- storing the machine readable specification of the cell in a computer readable memory,
- wherein said one or more nanowires or 2D material strips of the interconnect includes/include a set of nanowires or 2D material strips disposed in a plurality of stacks.
Dependencies are inferred from the claim text.