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US 9,355,966 B2Granted
Substrate warpage control using external frame stiffener
AssigneeAvago Technologies General IP (Singapore) Pte. Ltd.
InventorsAdam Gallegos, Walter J. Dauksher
Life of this patent
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Abstract
A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package.
Claims20
A semiconductor package, comprising:
- a substrate having a first major surface and an opposing second major surface;
- a semiconductor chip connected to the first major surface of the substrate via a plurality of electrically-conductive bumps;
- a lid connected to the first major surface of the substrate, wherein a connection between the lid and the first major surface of the substrate at least partially surrounds the chip and the plurality of electrically-conductive bumps, wherein the connection between the lid and the first major surface of the substrate is established at least at a perimeter of the first major surface of the substrate;
- a ball grid array established on the second major surface of the substrate;
- and
- a warpage control frame configured to control a warpage of the semiconductor package comprising:
- a perimeter section having a perimeter configured to match a perimeter of the substrate and the lid of the semiconductor package, the perimeter section further defining an internal void volume of the warpage control frame, wherein the perimeter section is configured to substantially surround the ball grid array such that a plurality of balls in the ball grid array structure are disposed within the internal void volume of the warpage control frame, the perimeter section comprising a thickness that is between 10% and 75% a height of the ball grid array structure;
- a first cross member that travels through the internal void volume separating the internal void volume into first and second internal void volumes such that the ball grid array structure is separated into a first plurality of balls disposed within the first internal void volume and a second plurality of balls disposed within the second internal void volume;
- and
- a second cross member that also travels through the internal void volume and intersects the first cross member such that the second cross member travels through the first and second internal void volumes further separating the first and second internal void volumes into smaller void volumes, wherein a divided plurality of balls in the ball grid array structure are disposed in each of the smaller void volumes.
7 more elements
A chip package, comprising:
- a semiconductor die;
- a substrate on which the semiconductor die is mounted;
- a lid that substantially seals the semiconductor die within a cavity established about the substrate, wherein the lid is attached to the substrate at least at a perimeter of the substrate;
- a ball grid array established on the substrate in opposition to the semiconductor die and the lid;
- and
- a warpage control frame connected to the substrate at least at the perimeter of the substrate and configured to prevent warpage of the substrate by providing mechanical reinforcement to the substrate on a side of the substrate opposite the attached lid, the warpage control frame comprising:
- a perimeter section having a perimeter configured to match the perimeter of the substrate and the lid of the chip package, the perimeter section further defining an internal void volume of the warpage control frame, wherein the perimeter section is configured to substantially surround the ball grid array such that a plurality of balls in the ball grid array structure are disposed within the internal void volume of the warpage control frame, the perimeter section comprising a thickness that is between 10% and 75% a height of the ball grid array structure;
- a first cross member that travels through the internal void volume separating the internal void volume into first and second internal void volumes such that the ball grid array structure is separated into a first plurality of balls disposed within the first internal void volume and a second plurality of balls disposed within the second internal void volume;
- and
- a second cross member that also travels through the internal void volume and intersects the first cross member such that the second cross member travels through the first and second internal void volumes further separating the first and second internal void volumes into smaller void volumes, wherein a divided plurality of balls in the ball grid array structure are disposed in each of the smaller void volumes.
7 more elements
A warpage control frame adapted for use in controlling warpage of a chip package having a ball grid array structure, the warpage control frame comprising:
- a perimeter section having a perimeter configured to match a perimeter of a substrate and lid of the chip package, the perimeter section further defining an internal void volume of the warpage control frame, wherein the perimeter section is configured to substantially surround the ball grid array structure such that a plurality of balls in the ball grid array structure are disposed within the internal void volume of the warpage control frame, the perimeter section comprising a thickness that is between 10% and 75% a height of the ball grid array structure;
- a first cross member that travels through the internal void volume separating the internal void volume into first and second internal void volumes such that the ball grid array structure is separated into a first plurality of balls disposed within the first internal void volume and a second plurality of balls disposed within the second internal void volume;
- and
- a second cross member that also travels through the internal void volume and intersects the first cross member such that the second cross member travels through the first and second internal void volumes further separating the first and second internal void volumes into smaller void volumes, wherein a divided plurality of balls in the ball grid array structure are disposed in each of the smaller void volumes.
1 more element
Dependencies are inferred from the claim text.