Instruction buffer bypass of target instruction in response to partial flush

A circuit arrangement, comprising:

• an instruction cache configured to fetch instructions from at least one instruction stream and concurrently output a plurality of instructions;
• a plurality of execution units configured to execute instructions from the instruction cache;
• a symmetric multithreaded (SMT) pipelined instruction unit implemented in hardware and coupled intermediate the instruction cache and the plurality of execution units, the multithreaded pipelined execution unit configured to concurrently dispatch a plurality of instructions from a plurality of threads associated with a plurality of instruction streams to the plurality of execution units, the SMT pipelined instruction unit including:
• an instruction buffer including a plurality of entries and a plurality of output ports, each entry configured to store an instruction awaiting dispatch to an execution unit, each entry including a valid indicator that indicates whether such entry currently stores a valid instruction awaiting dispatch, and each output port configured to output an instruction stored in one of the plurality of entries;
• a plurality of bypass multiplexers, each bypass multiplexer including a first input coupled to an output port among the plurality of output ports, a second input coupled to receive an instruction output by the instruction cache, and an output configured to output an instruction from one of the first and second inputs responsive to a select input;
• and
• dependency and issue logic including a plurality of input ports respectively configured to receive instructions output by the plurality of bypass multiplexers and selectively dispatch such instructions to the plurality of execution units, the dependency and issue logic configured to output demand information associated with a number of instructions requested by the dependency and issue logic in an upcoming cycle;
• and
• bypass logic configured to receive the valid indicators of the plurality of entries in the instruction buffer and the demand information from the dependency and issue logic, wherein the bypass logic is configured to, subsequent to a flush of the instruction buffer that results in the instruction buffer currently having buffered therein less than the number of instructions requested by the dependency and issue logic, control the select inputs of the plurality of bypass multiplexers to selectively cause at least one instruction received from the instruction cache to bypass the instruction buffer and be forwarded directly from the instruction cache to the dependency and issue logic;
• wherein the SMT pipelined instruction unit is further configured to, when a target instruction for a branch instruction is stored in the instruction buffer and a branch mispredict occurs for the branch instruction, perform a partial flush of the instruction buffer by flushing instructions in the instruction buffer that are older than the target instruction, and wherein the bypass logic is configured to cause the target instruction to be bypassed out-of-order from the instruction buffer in response to the partial flush of the instruction buffer.