Memory channel that supports near memory and far memory access
AssigneeIntel Corporation
InventorsBill Nale, Raj K. Ramanujan, Muthukumar P. Swaminathan, Tessil Thomas, Taarinya Polepeddi
Life of this patent
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Abstract
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic circuitry to implement a first memory channel protocol on the memory channel. The first memory channel protocol is specific to a first volatile system memory technology. The interface also includes second logic circuitry to implement a second memory channel protocol on the memory channel. The second memory channel protocol is specific to a second non volatile system memory technology. The second memory channel protocol is a transactional protocol.
Claims16
A method performed by logic circuitry disposed on a card having a connector to plug into a memory channel that supports near memory cache accesses and far memory accesses, comprising:
- receiving from said memory channel a first tag component of a target address of a read request transaction being processed by a host that is coupled to said memory channel;
- receiving a second tag component of an address of a cache line read from a near memory cache in response to said read request transaction;
- and,
- comparing said first and second tag components to determine if said cache line corresponds to a cache hit or a cache miss.
A semiconductor chip, comprising:
- an interface to a memory channel;
- a read buffer to hold a far memory read request received from said memory channel;
- logic circuitry to detect a cache miss of a cache line read from a near memory in response to a near memory read request issued on said memory channel, said near memory a cache for said far memory, said logic circuitry to additionally perform at least one of the following in response thereto:
- initiate a read of a desired cache line from said far memory, said desired cache line containing data sought by a transaction that caused said near memory read request to be issued on said memory channel;
- detect that a dirty bit of said cache line read from near memory is set and automatically writing said cache line read from said near memory into far memory.
Dependencies are inferred from the claim text.