Capacitor array and layout design method thereof

A layout design method of a capacitor array, wherein the capacitor array comprises first class capacitors to Kth class capacitors, K is an integer no less than 1, each capacitor comprises several unit capacitors, the design method comprises:

• defining a wiring mode of the unit capacitors:
• made a wire connected to a upper plate be parallel with a wire connected to a lower one, and the wires connected to the lower plate of each unit capacitor are the same kind of metal being designed symmetrically on the both sides of each unit capacitor, the wires connected to the upper plate of each unit capacitor are the same kind of metal being centered at each unit capacitor;
• defining the layout of the capacitor array:
• the capacitor array comprises M lines and N rows, wherein the capacitor array consists of an inner capacitor array and an external dummy capacitor array, the external dummy capacitor array is designed around the inner capacitor array being made up of a plurality of dummy capacitors, the inner capacitor array comprises two symmetric unilateral inner capacitor arrays, (a) Mh is defined as the maximum number of lines of the inner capacitor array and expressed as Mh=M/2−Mdx, wherein Mh is an integer, Mdx denotes the line number of the external dummy capacitor array, Mdx≧1.5, (b) the line numbers of the first class to the Kth class capacitors are defined for the inner capacitor array, (c) the capacitors are placed on the layout wherein the sum of the line numbers of the first class to the Kth class capacitors is no more than Mh and no more than two wiring modes are used for the capacitors in each line;
• wiring the capacitor array:
• the wiring mode is set for the capacitor array requiring that the lengths of the paralleled wires being connected to the upper and lower plates of each unit capacitor are equal;
• and
• parasitic parameters are characterized in ways that verify the layout design.