Method for low temperature bonding and bonded structure

A bonded structure, comprising:

• a processed semiconductor device wafer comprising a first surface having a thickness, a planarized insulating material of deposited silicon oxide having a first bonding surface, wherein said planarized insulating material is opposite said first surface, and a device layer between said first surface and said planarized insulating material;
• a first material comprising silicon having a second surface and a second bonding surface opposite said second surface, wherein no devices are disposed in said first material;
• wherein said first bonding surface is an etched surface terminated with nitrogen;
• wherein said first and second bonding surfaces are in direct contact with each other and bonded together with a chemical bond without any adhesive;
• wherein said device layer comprises CMOS circuitry and includes at least one insulating layer;
• wherein said first surface is one surface of a thinned silicon substrate;
• wherein said first surface includes a photolithographic mask on at least a portion thereof;
• and
• wherein said etched surface has a RMS surface roughness of between abut 0.1 and 3.0 nm.

A bonded structure, comprising:

• a first silicon material comprising a first surface and a planarized insulating material having a first bonding surface wherein said planarized insulating material is opposite said first surface;
• a second material having a second surface and a second bonding surface opposite said second surface, wherein no devices are disposed in said second material;
• wherein said first bonding surface is an etched surface terminated with a species;
• and
• wherein said first and second bonding surfaces are in direct contact with each other and bonded together with a chemical bond without any adhesive.

A bonded structure, comprising:

• a first silicon material comprising a first surface having a thickness, a planarized insulating material of deposited silicon oxide having a first bonding surface, wherein said planarized insulating material is opposite said first surface, and a device layer between said first surface and said planarized insulating material;
• a second material comprising silicon having a second surface and a second bonding surface opposite said second surface, wherein no devices are disposed in said second material;
• wherein said first bonding surface is an etched surface terminated with nitrogen;
• wherein said first and second bonding surfaces are in direct contact with each other and bonded together with a chemical bond without any adhesive;
• wherein said device layer comprises CMOS circuitry and includes at least one insulating layer;
• wherein said first surface is one surface of a thinned silicon substrate;
• wherein said first surface includes a photolithographic mask on at least a portion thereof;
• and
• wherein said etched surface has a RMS surface roughness of between abut 0.1 and 3.0 nm.