Voltage controlled oscillator including MuGFETS

A system for an integrated circuit device, comprising:

• a controller configured to receive a frequency and amplitude swing input signal;
• and
• a voltage controlled oscillator coupled to the controller and configured to receive selection signals and a control voltage;
• wherein the voltage controlled oscillator comprises:
• an inductor having a tap and having or coupled to a positive-side output node and a negative side output node, wherein the tap is configured to receive a first current;
• a coarse grain capacitor array coupled to the positive-side output node and the negative side output node and configured to respectively receive the select signals;
• a varactor coupled to the positive-side output node and the negative side output node and configured to receive the control voltage, wherein the varactor includes first MuGFETs;
• a transconductance cell coupled to the positive-side output node and the negative side output node and having a common node;
• and
• a frequency scaled resistor network coupled to the common node and configured to receive the select signals for resistance of a path for a second current;
• wherein:
• cells of the coarse grain capacitor array are spaced apart from one another as coupled to the positive-side output node and the negative side output node;
• the cells are progressively spaced away from a coil of the inductor;
• and
• groups of select transistors of the cells are configured to respectively receive the select signals.

A method for voltage controlled oscillation, comprising:

• receiving a first current to a tap of an inductor;
• wherein the inductor is coupled to or has a positive-side output node and a negative side output node;
• selecting a capacitance from a coarse grain capacitor array coupled to the positive-side output node and the negative side output node;
• wherein the coarse grain capacitor array is configured to respectively receive select signals to select the capacitance;
• wherein:
• cells of the coarse grain capacitor array are spaced apart from one another as coupled to the positive-side output node and the negative side output node;
• and
• the cells are progressively spaced away from a coil of the inductor;
• respectively receiving the select signals by groups of select transistors of the cells to select the capacitance;
• setting a control voltage for a varactor coupled to the positive-side output node and the negative side output node;
• wherein the varactor includes MuGFETs;
• providing transconductance via a transconductance cell coupled to the positive-side output node and the negative side output node;
• wherein the transconductance cell has a common node;
• selecting a resistance from a frequency scaled resistor network coupled to the common node for a path for a second current;
• wherein the frequency scaled bias current source-resistor network is configured to receive the select signals to select the resistance for the path;
• and
• outputting an oscillating signal.