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US 9,324,698 B2Granted
Multi-chip structure and method of forming same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChen-Hua Yu, Der-Chyang Yeh
Life of this patent
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Abstract
A device comprises a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer. The device further comprises a redistribution layer formed on a top surface of a first side of the encapsulation layer, wherein the redistribution layer is connected to active circuits of the first chip and the second chip and the redistribution layer extends beyond at least one edge of the first chip and the second chip.
Claims20
A device comprising:
- a fan-out structure comprising:
- a redistribution layer disposed on a first side of the fan-out structure;
- a dielectric layer disposed over the redistribution layer;
- and
- a plurality of first bumps disposed over the dielectric layer and on a second side of the fan-out structure;
- a first chip disposed over the first side of the fan-out structure, wherein the first chip comprise a plurality of first through vias connected to the redistribution layer;
- a second chip disposed over the first chip, wherein:
- the second chip is connected to the first chip through a plurality of second bumps;
- and
- a molding compound layer disposed over the first side of the fan-out structure, wherein the first chip and the second chip are embedded in the molding compound layer, and wherein at least one edge of the first chip is not vertically aligned with a corresponding edge of the second chip.
7 more elements
A device comprising:
- a first chip and a second chip stacked together to form a multi-chip structure, wherein the multi-chip structure is embedded in an encapsulation layer, and wherein at least one edge of the first chip is not vertically aligned with a corresponding edge of the second chip, and wherein at least one sidewall of the first chip and the second chip is exposed outside the encapsulation layer;
- a redistribution layer disposed on a top surface of a first side of the encapsulation layer, wherein:
- the redistribution layer is connected to active circuits of the first chip and the second chip;
- and
- the redistribution layer extends beyond at least one edge of the first chip and the second chip;
- and
- a plurality of conductive bumps disposed over the redistribution layer and connected to the redistribution layer.
4 more elements
A method comprising:
- attaching a plurality of stacked semiconductor dies on a carrier through an adhesive layer;
- mounting a semiconductor chip on a top surface of the plurality of stacked semiconductor dies;
- forming a molding compound layer over the carrier, wherein the plurality of stacked semiconductor dies and the semiconductor chip are embedded in the molding compound layer, and wherein at least one edge of the stacked semiconductor dies is not vertically aligned with a corresponding edge of the semiconductor chip;
- grinding the molding compound layer until a surface of the semiconductor chip is exposed;
- forming a redistribution layer on the surface of the semiconductor chip;
- and
- forming a plurality of conductive bumps over the redistribution layer.
4 more elements
Dependencies are inferred from the claim text.