Circuit and system for concurrently programming multiple bits of OTP memory devices

An One-Time Programmable (OTP) memory capable of concurrent multi-bit programming, comprising:

• a plurality of OTP cells, each of the OTP cells including (i) an electrical fuse element as an OTP element, and (ii) a diode as program selector having at least a first active region with a first type of dopant to provide a first terminal of the diode, and a second active region with a second type of dopant to provide a second terminal of the diode, both active regions being fabricated from sources or drains of CMOS devices and residing in a common CMOS well, the first terminal of the diode coupled to a first terminal of the OTP element;
• a plurality of local wordlines, each coupled to a plurality of the OTP cells via the second terminal of the diodes;
• a plurality of global wordlines, each coupled to at least one of the local wordlines;
• and
• a plurality of bitlines arranged in banks, each bitline coupled to a plurality of the OTP cells via a second terminal of the OTP element;
• and.
• wherein a plurality of OTP elements being configured to be concurrently programmable by applying at least one voltage to at least one wordline and at least one bitline coupled to a plurality of the OTP cells in a plurality of the banks.

An electronics system, comprising:

• a processor;
• and
• at least one multiple-bit concurrently programmable OTP memory operatively connected to the processor, the OTP memory comprising:
• a plurality of OTP cells, each including an electrical fuse element coupled to a program selector, the program selector having a control terminal;
• a plurality of local wordlines, each coupled to a plurality of the OTP cells via the control terminal of the program selector;
• a plurality of global wordlines, each coupled to at least one of the local wordlines;
• and
• a plurality of bitlines arranged in banks, each bitline coupled to a plurality of OTP cells in a bank;
• a plurality of bank selects to enable turning on the wordlines or bitlines in a bank;
• and
• wherein a plurality of OTP cells can be configured to be concurrently programmable by applying at least one voltage to at least one wordline and at least one bitline in a plurality of the banks if a plurality of the bank selects corresponding to the plurality of the banks are asserted.

A method for operating a programmable OTP memory, comprising:

• providing a plurality of OTP cells, each including an electrical fuse element coupled to a program selector, the program selector having a control terminal;
• providing a plurality of local wordlines, each coupled to a plurality of the OTP cells via the control terminal of the program selector;
• providing a plurality of global wordlines, each coupled to at least one of the local wordlines;
• providing a plurality bitlines arranged in banks, each bitline coupled to a plurality of the OTP cells;
• and
• concurrently programming a plurality of selected OTP cells into a different logic state by applying voltages to at least one selected global wordlines and at least one selected bitlines in a plurality of the banks to conduct currents and change the resistance of the selected OTP cells.