Mechanism for wire-speed stateful packet inspection in packet processors

A packet processor comprising:

• an extraction circuit configured to generate a first set of values based on a first packet;
• a lookup circuit configured to store a plurality of metadata values, wherein each metadata value of the plurality of metadata values corresponds to a respective metadata identifier of a plurality of unique metadata identifiers;
• an assignment circuit configured to assign a first metadata identifier to the first packet, wherein the lookup circuit is configured to selectively retrieve a first metadata value of the plurality of metadata values that corresponds to the first metadata identifier;
• a rule matching circuit configured to select a first rule from among a predetermined set of rules based on (i) the first set of values and (ii) the first metadata value of the plurality of metadata values;
• and
• an action circuit configured to (i) identify a first action specified by the first rule of the predetermined set of rules and (ii) perform the first action, wherein the first action includes modifying the first metadata value of the plurality of metadata values.