Decision feedback equalizer using current mode processing with CMOS compatible output level

An equalizer system, said system comprising:

• a degeneration amplifier comprising a current output;
• a plurality of current summer core pairs, coupled to said degeneration amplifier, that are a part of a plurality of systems for processing a signal received from said degeneration amplifier, wherein at least one of said plurality of systems comprise:
• a current summer core comprising a current mirror, that in current mode, is operable to remove inter-symbol interference from a signal, wherein said current output is connect to said current mirror directly;
• and
• a CMOS latch component coupled to said current summer core, that is operable to receive a current mode signal and outputs a CMOS compatible signal, wherein components of said decision feedback equalizer system are controlled by a single clock and wherein said current summer core provides current mode signal processing and said CMOS latch component provides a CMOS compatible output level.

A method of operating a decision feedback equalizer system, said method comprising:

• receiving a bit of data into a current summer core of said decision feedback equalizer system;
• receiving into said current summer core a determined measure of inter-symbol interference;
• subtracting said determined measure of inter-symbol interference from said bit of data to generate an equalized data bit;
• providing said equalized data bit to a CMOS latch that is directly coupled to a current mirror of said current summer core;
• and
• providing access to said equalized data bit at a CMOS compatible level wherein said current summer core provides current mode signal processing and said CMOS latch component provides said CMOS compatible output level.