Multi-wire signaling with matched propagation delay among wire pairs
AssigneeQUALCOMM Incorporated
InventorsShree Krishna Pandey, Arun Chandra Kundu, George Alan Wiley, Chulkyu Lee
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Abstract
In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.
Claims43
An apparatus for multi-wire signaling, comprising:
- a plurality of wires comprising at least three wires;
- and
- at least one delay element coupled to at least one of the plurality of wires, the at least one delay element to provide an amount of signal delay such that a signal propagation time associated with a wire of the plurality of wires is unequal to a signal propagation time associated with another wire of the plurality of wires and signal propagation times associated with wire pairs of the plurality of wires are equal to one another within a margin of error.
A method for multi-wire signaling, comprising:
- determining signal propagation times associated with wire pairs of a plurality of wires, the plurality of wires comprising at least three wires;
- and
- specifying a delay for at least one delay element coupled to at least one of the wires such that a signal propagation time associated with a wire of the plurality of wires is unequal to a signal propagation time associated with another wire of the plurality of wires and the signal propagation times associated with the wire pairs of the plurality of wires are equal to one another within a margin of error.
An apparatus for multi-wire signaling, comprising:
- a memory device;
- a processing circuit coupled to the memory device and configured to:
- determine signal propagation times associated with wire pairs of a plurality of wires, the plurality of wires comprising at least three wires;
- and
- specify a delay for at least one delay element coupled to at least one of the wires such that a signal propagation time associated with a wire of the plurality of wires is unequal to a signal propagation time associated with another wire of the plurality of wires and the signal propagation times associated with the wire pairs of the plurality of wires are equal to one another within a margin of error.
An apparatus for multi-wire signaling, comprising:
- means for determining signal propagation times associated with wire pairs of a plurality of wires, the plurality of wires comprising at least three wires;
- and
- means for specifying a delay for at least one delay element coupled to at least one of the wires such that a signal propagation time associated with a wire of the plurality of wires is unequal to a signal propagation time associated with another wire of the plurality of wires and the signal propagation times associated with the wire pairs of the plurality of wires are equal to one another within a margin of error.
An apparatus for multi-wire signaling, comprising:
- a transmitter;
- a receiver,
- a plurality of wires comprising at least three wires coupled to the transmitter and the receiver;
- and
- at least one delay element coupled to at least one of the wires, the at least one delay element to provide an amount of signal delay such that a signal propagation time associated with a wire of the plurality of wires is unequal to a signal propagation time associated with another wire of the plurality of wires and signal propagation times associated with wire pairs of the plurality of wires are equal to one another within a margin of error,
- wherein the transmitter is configured to, for a particular data transfer, drive a particular one of the wire pairs of the plurality of wires, whereby every other wire of the plurality of wires is in a high impedance state.
Dependencies are inferred from the claim text.