Receiver eye-monitor circuit and method

A method of obtaining bit error data for an eye-opening diagram by on-die instrumentation, the method comprising:

• selecting, by a voltage multiplexer, a reference voltage from a high reference voltage and a low reference voltage;
• selecting, by a clock multiplexer, a clock signal from an even clock signal and an odd clock signal;
• slicing an input data signal by a first sense amplifier circuit using a first slicing voltage at times indicated by said clock signal to generate a speculative-high error signal, wherein said first slicing voltage comprises said reference voltage increased by a speculative voltage;
• and
• slicing the input data signal by a second sense amplifier circuit using a second slicing voltage at times indicated by said clock signal to generate a speculative-low error signal, wherein said second slicing voltage comprises said reference voltage reduced by the speculative voltage.

A method performed by on-die instrumentation, the method comprising:

• generating speculative-high and speculative-low error signals using first and second sense amplifiers, respectively;
• deserializing the speculative-high and speculative-low error signals to generate speculative-high and speculative-low error data;
• and
• determining bits in the speculation-high and speculation-low error data that are invalid based on prior bits in recovered data obtained using a clock-data recovery and decision feedback equalizer circuit.