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AssigneeCypress Semiconductor Corporation
InventorsAkira Shimamura, Koichi Mita, Takashi Arai, Hideshi Fujishima, Akira Endo
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A signal processor includes a period detection section which detects that a period is currently used for communication of a frame; a pattern detection section which detects, from the received signal, a first signal pattern by which the end of communication of the frame is recognized; and an output processing section which outputs the received signal to a controller; configured to instruct, upon detection of the first signal pattern in the period being currently used for communication of a frame, the controller to halt startup of communication action of the next frame, until the period being currently used for communication of a frame comes to the end, to thereby reduce an event such that frames are transmitted from a plurality of communication devices simultaneously, and to thereby allow the communication action for the next frame to proceed correctly.
A signal processor configured to allow a communication device to recognize the end of communication of a frame, based on a received signal, and to start a communication action of a next frame, the signal processor comprising:
A communication device allowing frame communication to proceed based on allocated unit communication periods, so as to start a communication action of a next frame upon recognition of the end of communication of a frame based on a received signal, the communication device comprising:
Dependencies are inferred from the claim text.