DSSS inverted spreading for smart utility networks
AssigneeTexas Instruments Incorporated
InventorsTimothy Mark Schmidl, Anand G. Dabak
Life of this patent
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Abstract
A method of operating a transmitter (FIGS. 3A and 5A) is disclosed. The method includes receiving a sequence of data bits (DATA), wherein each data bit has a respective sequence number. A first data bit of the sequence is spread (508) with a first spreading code (504) determined by the sequence number (502) of the first data bit. A second data bit of the sequence is spread (508) with an inverse of the first spreading code (506) determined by the sequence number (502) of the second data bit. The first and second data bits are modulated (510) and transmitted (516) to a remote receiver.
Claims20
A transmitter, comprising:
- a buffer configured to receive a sequence of data bits, each data bit having a respective sequence number;
- a memory circuit storing a first spreading code and a second spreading code inversing the first spreading code;
- and
- an XOR circuit coupled with the buffer, the XOR circuit configured to:
- spread a first data bit of the sequence into spread first data bits using the first spreading code determined by the sequence number of the first data bit;
- and
- spread a second data bit of the sequence into spread second data bits using the second spreading code determined by the sequence number of the second data bit.
A transmitter, comprising:
- a buffer configured to receive a sequence of data bits, each data bit having a respective sequence number;
- an inverter coupled with the buffer, the inverter configured to invert a first data bit of the sequence in response to the sequence number of the first data bit;
- and
- an XOR circuit alternately coupled with the buffer and the inverter to:
- spread the inverted first data bit into spread first data bits using a spreading code;
- and
- spread a second data bit into spread second data bits of the sequence using the spreading code.
A receiver, comprising:
- a memory circuit storing a first despreading code and a second despreading code inversing the first despreading code;
- and
- an XOR circuit coupled with the memory circuit, the XOR circuit configured to:
- receive a first and second groups of spread data bits, each group of spread data bits having a respective sequence number;
- despread the first group of spread data bits sharing a first sequence number to generate a first data bit using the first despreading code determined by the first sequence number;
- and
- despread the second group of spread data bits to generate a second data bit using the second despreading code.
A receiver, comprising:
- a memory circuit storing a despreading code;
- an XOR circuit coupled with the memory circuit, the XOR circuit configured to:
- receive a first and second groups of spread data bits, each group of spread data bits having a respective sequence number;
- despread the first group of spread data bits to generate a first data bit using a spreading code;
- and
- despread the second group of spread data bits to generate a second data bit using the spreading code;
- and
- an inverter coupled with the XOR circuit, the inverter configured to invert the second data bit in response to the sequence number of the second group of spread data bits.
Dependencies are inferred from the claim text.