Calibrated SAR ADC having a reduced size

A SAR ADC comprising:

• a DAC having a capacitor array, the capacitor array having a plurality of segments, and a number of attenuation capacitors that are connected to the plurality of segments such that an attenuation capacitor is connected to and between each adjacent pair of segments, the plurality of segments including:
• a main DAC segment having a number of binary-weighted main conversion capacitors, none of the number of binary-weighted main conversion capacitors having substantially identical weights;
• one or more sub-DAC segments having a number of binary-weighted sub-DAC capacitors, one sub-DAC segment having three binary-weighted sub-DAC capacitors that have substantially identical weights;
• a comparator connected to the DAC;
• and
• a controller connected to the DAC and the comparator;
• further comprising a differential DAC that is connected to the comparator and the controller, the differential DAC having a differential capacitor array, the differential capacitor array having a plurality of differential segments, and a number of differential attenuation capacitors that are connected to the plurality of differential segments such that a differential attenuation capacitor is connected to and between each adjacent pair of differential segments, the plurality of differential segments including:
• a differential main DAC segment having a number of binary-weighted differential main conversion capacitors, none of the number of binary-weighted differential main conversion capacitors having substantially identical weights;
• one or more differential sub-DAC segments having a number of binary-weighted differential sub-DAC capacitors, one differential sub-DAC segment having three binary-weighted differential sub-DAC capacitors that have substantially identical weights.

A method of calibrating a SAR ADC comprising:

• closing a ground switch;
• connecting a reference voltage to a first selected number of capacitors of a plurality of capacitors, and ground to a first remaining number of capacitors of the plurality of capacitors, the first selected number of capacitors excluding a main conversion capacitor that is being calibrated and any previous main conversion capacitors that have been calibrated, each of the plurality of capacitors having a specified capacitance, a sum of the specified capacitances of the first selected number of capacitors adding up to a first value;
• opening the ground switch after the reference voltage has been connected to the first selected number of capacitors, and ground to the first remaining number of capacitors;
• connecting the reference voltage to a second selected number of capacitors of the plurality of capacitors, and ground to a second remaining number of capacitors of the plurality of capacitors to generate a first DAC voltage after the ground switch has been opened, the second selected number of capacitors including the main conversion capacitor that is being calibrated, and excluding any previous main conversion capacitors that have been calibrated, a sum of the specified capacitances of the second selected number of capacitors adding up to a second value that is equal to the first value.

A method of operating a SAR ADC comprising:

• first determining a logic value for a most significant bit (MSB) within a digital word, the first determining including:
• connecting an input voltage to a first plurality of capacitors, the first plurality of capacitors including a plurality of main conversion capacitors, a plurality of sub-conversion capacitors, and a plurality of shared capacitors;
• and
• connecting a reference voltage to a second plurality of capacitors, the second plurality of capacitors including a main conversion capacitor of the plurality of main conversion capacitors, and a first selected number of shared capacitors of the plurality of shared capacitors to generate a MSB DAC voltage;
• and
• second determining a logic value for a least significant bit (LSB) within the digital word, the second determining including connecting the reference voltage to a second selected number of shared capacitors from the plurality of shared capacitors to generate a LSB DAC voltage.