Phase-locked loop (PLL)

A phase-locked loop (PLL), comprising:

• a spur-cancel control circuit comprising:
• a bit selector configured to:
• receive a frequency command word (FCW) signal;
• and
• generate a modified FCW signal representing a fractional part of a FCW represented by the FCW signal;
• and
• a comparator configured to generate an enable signal based on the modified FCW signal;
• a dithering circuit configured to:
• receive a first tuning signal and the enable signal;
• and
• dither the first tuning signal based on the enable signal to generate a dither signal;
• and
• a digitally controlled oscillator (DCO) configured to:
• receive a DCO input signal generated based on at least one of the dither signal or a second tuning signal;
• and
• generate an output signal having an output frequency based on the DCO input signal.

A phase-locked loop (PLL), comprising:

• a phase error circuit comprising a subtractor and configured to:
• receive a reference phase signal representing a reference phase;
• receive a first output phase signal representing a fractional part of an output phase of an output signal;
• receive a second output phase signal representing an integer part of the output phase;
• and
• subtract the fractional part of the output phase and the integer part of the output phase from the reference phase to generate a phase error signal;
• a dithering circuit configured to:
• receive a first tuning signal generated based on the phase error signal;
• and
• dither the first tuning signal to generate a dither signal;
• and
• a digitally controlled oscillator (DCO) configured to:
• receive a DCO input signal generated based on at least one of the dither signal or a second tuning signal;
• and
• generate the output signal having an output frequency based on the DCO input signal.

A phase-locked loop (PLL), comprising:

• a spur-cancel control circuit comprising:
• a clock adjuster configured to:
• receive an initial clock signal having an initial frequency;
• and
• modify the initial clock signal to a first modified clock signal having a modified frequency;
• a multiplexer configured to:
• receive an enable signal generated based on a frequency command word (FCW) signal;
• receive the first modified clock signal;
• receive the initial clock signal;
• and
• generate a second modified clock signal having the modified frequency when the enable signal has a first value and having the initial frequency when the enable signal has a second value;
• a dithering circuit configured to:
• receive a first tuning signal and the enable signal;
• and
• dither the first tuning signal based on the enable signal to generate a dither signal;
• and
• a digitally controlled oscillator (DCO) configured to:
• receive a DCO input signal generated based on at least one of the dither signal or a second tuning signal;
• and
• generate an output signal having an output frequency based on the DCO input signal.