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US 9,319,048 B2Granted
Clock divider
AssigneeMarvell World Trade Ltd.
InventorElad Lifshitz
Life of this patent
Estimating the term…
Abstract
Aspects of the disclosure provide a circuit including a logic circuit. The logic circuit is configured to operate without inputs from a first clock signal. The logic circuit is further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry driven by the first clock signal, and a second pattern provided by a second circuitry driven by the first clock signal.
Claims12
A circuit, comprising:
- a logic circuit configured to operate without inputs from a first clock signal, the logic circuit being further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry including a first sampling flip-flop driven by the first clock signal, and a second pattern provided by a second circuitry including a second sampling flip-flop driven by an inversed first clock signal, the first sampling flip-flop and the second sampling flip-flop having a substantially equal delay in response input clocks;
- and
- a first inverter configured to inverse the first clock signal to generate the inversed first clock signal, a delay of the first inverter being compensated by a second inverter of the first circuitry.
A method for clock generation, comprising:
- receiving a first pattern provided by a first circuitry driven by a first clock signal;
- receiving a second pattern provided by a second circuitry driven by the first clock signal;
- logic-combining, using a logic circuit that is configured to operate without receiving an input from the first clock signal, the first pattern and the second pattern to frequency-divide the first clock signal to generate a second clock signal;
- providing the first clock signal to a first sampling flip-flop in the first circuitry;
- providing an inversed first clock signal to a second sampling flip-flop in the second circuitry, the second sampling flip-flop having a substantially equal delay in response to input clocks as the first sampling flip-flop;
- inversing, by a first inverter, the first clock signal to generate the inversed first clock signal;
- and
- compensating, using a second inverter in the first circuitry, a delay of the first inverter.
5 more elements
An integrated circuit (IC) chip, comprising:
- a clock generator configured to generate a first clock signal;
- and
- a clock divider comprising:
- a first circuitry configured to drive a first pattern in response to the first clock signal, the first circuitry including a first sampling flip-flop driven by the first clock signal;
- a second circuitry configured to drive a second pattern in response to the first clock signal, the second circuit including a second sampling flip-flop driven by an inversed first clock signal, the first sampling flip-flop and the second sampling flip-flop having a substantially equal delay in response input clocks;
- a first inverter configured to inverse the first clock signal to generate the inversed first clock signal, a delay of the first inverter being compensated by a second inverter of the first circuitry;
- and
- a logic circuit configured to operate without inputs from the first clock signal, and to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of the first pattern and the second pattern.
5 more elements
A circuit, comprising:
- a logic circuit configured to operate without inputs from a first clock signal, the logic circuit being further configured to frequency-divide the first clock signal to generate a second clock signal based on a logic combination of a first pattern provided by a first circuitry driven by the first clock signal, and a second pattern provided by a second circuitry driven by a signal that is acquired by an inversion of the first clock signal, the first circuitry being configured to compensate a delay caused by the inversion.
Dependencies are inferred from the claim text.