Method and apparatus for reducing gate leakage of low threshold transistors during low power mode in a multi-power-domain chip

A method for reducing gate leakage current in a switchable power domain of a CMOS (complementary metal oxide semiconductor) integrated circuit chip, the method comprising:

• (a) coupling a drain electrode of a first transistor to a first terminal of a power switch having a second terminal coupled to a first reference voltage, and coupling a body electrode and a source electrode of the first transistor to a second reference voltage, the first transistor having a gate electrode and a relatively high first gate leakage current that flows from its gate electrode to its body electrode if the power switch is open and a voltage of the gate electrode of the first transistor resenting a first logic level exceeds a voltage of the body electrode by more than a first predetermined amount;
• and
• (b) producing a relatively low voltage on the gate electrode of the first transistor representing a second logic level to substantially reduce the first gate leakage current when reduced power consumption of the chip is needed.

A circuit for reducing gate leakage current in a switchable power domain of a CMOS (complementary metal oxide semiconductor) integrated circuit chip, comprising:

• (a) means in the switchable power domain for coupling a drain electrode of a first transistor to a first terminal of a power switch having a second terminal coupled to a first reference voltage and coupling a body electrode and a source electrode of the first transistor to a second reference voltage, the first transistor having a gate electrode and a relatively high first gate leakage current that flows from its gate electrode to its body electrode if the power switch is open and a voltage of the gate electrode of the first transistor representing a first logic level exceeds a voltage of the body electrode by more than a first predetermined amount;
• and
• (b) means in the switchable power domain for producing a relatively low voltage on the gate electrode of the first transistor representing a second logic level to substantially reduce the first gate leakage current when reduced power consumption of the chip is needed.